7f4f696f10
It's not valid to set BYPASS and LDOEN at the same time. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
225 lines
7.6 KiB
C
225 lines
7.6 KiB
C
// Code to setup clocks on stm32h7
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//
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// Copyright (C) 2020 Konstantin Vogel <konstantin.vogel@gmx.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
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#include "board/armcm_boot.h" // VectorTable
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#include "board/armcm_reset.h" // try_request_canboot
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#include "board/irq.h" // irq_disable
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#include "board/misc.h" // bootloader_request
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // get_pclock_frequency
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#include "sched.h" // sched_main
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/****************************************************************
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* Clock setup
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****************************************************************/
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 4)
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// Map a peripheral address to its enable bits
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struct cline
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lookup_clock_line(uint32_t periph_base)
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{
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if (periph_base >= D3_AHB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D3_AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB4ENR, .rst=&RCC->AHB4RSTR, .bit=bit};
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} else if (periph_base >= D3_APB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D3_APB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB4ENR, .rst=&RCC->APB4RSTR, .bit=bit};
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} else if (periph_base >= D1_AHB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D1_AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB3ENR, .rst=&RCC->AHB3RSTR, .bit=bit};
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} else if (periph_base >= D1_APB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D1_APB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB3ENR, .rst=&RCC->APB3RSTR, .bit=bit};
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} else if (periph_base >= D2_AHB2PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D2_AHB2PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB2ENR, .rst=&RCC->AHB2RSTR, .bit=bit};
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} else if (periph_base >= D2_AHB1PERIPH_BASE) {
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if (periph_base == ADC12_COMMON_BASE)
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return (struct cline){.en = &RCC->AHB1ENR, .rst = &RCC->AHB1RSTR,
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.bit = RCC_AHB1ENR_ADC12EN};
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uint32_t bit = 1 << ((periph_base - D2_AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB1ENR, .rst=&RCC->AHB1RSTR, .bit=bit};
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} else if (periph_base >= D2_APB2PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D2_APB2PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit};
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} else {
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uint32_t offset = ((periph_base - D2_APB1PERIPH_BASE) / 0x400);
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if (offset < 32) {
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uint32_t bit = 1 << offset;
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return (struct cline){
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.en=&RCC->APB1LENR, .rst=&RCC->APB1LRSTR, .bit=bit};
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} else {
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uint32_t bit = 1 << (offset - 32);
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return (struct cline){
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.en=&RCC->APB1HENR, .rst=&RCC->APB1HRSTR, .bit=bit};
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}
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}
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}
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// Return the frequency of the given peripheral clock
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uint32_t
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get_pclock_frequency(uint32_t periph_base)
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{
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return FREQ_PERIPH;
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}
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// Enable a GPIO peripheral clock
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void
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gpio_clock_enable(GPIO_TypeDef *regs)
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{
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uint32_t pos = ((uint32_t)regs - D3_AHB1PERIPH_BASE) / 0x400;
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RCC->AHB4ENR |= (1<<pos);
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RCC->AHB4ENR;
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}
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#if !CONFIG_STM32_CLOCK_REF_INTERNAL
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DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
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#endif
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// Main clock and power setup called at chip startup
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static void
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clock_setup(void)
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{
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// Enable low dropout regulator
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PWR->CR3 = PWR_CR3_LDOEN;
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while (!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY))
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;
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// Setup pll1 frequency
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uint32_t pll_base = CONFIG_STM32_CLOCK_REF_25M ? 5000000 : 4000000;
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uint32_t pll_freq = CONFIG_CLOCK_FREQ * (CONFIG_MACH_STM32H723 ? 1 : 2);
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uint32_t rcc_cr = RCC_CR_HSION;
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if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
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// Configure PLL from external crystal (HSE)
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RCC->CR = rcc_cr = rcc_cr | RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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;
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RCC->PLLCKSELR = RCC_PLLCKSELR_PLLSRC_HSE
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| ((CONFIG_CLOCK_REF_FREQ/pll_base) << RCC_PLLCKSELR_DIVM1_Pos);
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} else {
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// Configure PLL from internal 64Mhz oscillator (HSI)
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// HSI frequency of 64Mhz is integer divisible with 4Mhz
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pll_base = 4000000;
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RCC->PLLCKSELR = RCC_PLLCKSELR_PLLSRC_HSI
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| ((64000000/pll_base) << RCC_PLLCKSELR_DIVM1_Pos);
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}
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// Set input frequency range of PLL1 according to pll_base
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// 3 = 8-16Mhz, 2 = 4-8Mhz
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RCC->PLLCFGR = (2 << RCC_PLLCFGR_PLL1RGE_Pos)
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// Enable PLL1Q (used by some peripherals)
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| RCC_PLLCFGR_DIVQ1EN
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// Enable PLL1P (for cpu clock)
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| RCC_PLLCFGR_DIVP1EN;
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// Set multiplier DIVN1 and post divider DIVP1
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RCC->PLL1DIVR = ((pll_freq/pll_base - 1) << RCC_PLL1DIVR_N1_Pos)
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// Set PLL1Q frequency (some peripherals directly use pll1_q_ck)
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| ((pll_freq/FREQ_PERIPH - 1) << RCC_PLL1DIVR_Q1_Pos)
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// Set PLL1P cpu clock frequency
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| ((pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLL1DIVR_P1_Pos);
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// Enable VOS1 power mode
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PWR->D3CR = 3 << PWR_D3CR_VOS_Pos;
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while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
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;
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// Enable VOS0 (overdrive) on stm32h743/stm32h750
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#if !CONFIG_MACH_STM32H723
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if (CONFIG_CLOCK_FREQ > 400000000) {
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enable_pclock((uint32_t)SYSCFG);
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SYSCFG->PWRCR |= SYSCFG_PWRCR_ODEN;
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while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
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;
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}
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#endif
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SCB_EnableICache();
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SCB_EnableDCache();
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// Set flash latency according to clock frequency
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uint32_t flash_acr_latency = (CONFIG_CLOCK_FREQ > 450000000) ?
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FLASH_ACR_LATENCY_4WS : FLASH_ACR_LATENCY_2WS;
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FLASH->ACR = flash_acr_latency | (2 << FLASH_ACR_WRHIGHFREQ_Pos);
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while (!(FLASH->ACR & flash_acr_latency))
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;
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// Set HPRE clock to div 2 (CONFIG_CLOCK_FREQ/2) and set
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// peripheral clocks another div 2 (CONFIG_CLOCK_FREQ/4)
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RCC->D1CFGR = RCC_D1CFGR_HPRE_DIV2 | RCC_D1CFGR_D1PPRE_DIV2;
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RCC->D2CFGR = RCC_D2CFGR_D2PPRE1_DIV2 | RCC_D2CFGR_D2PPRE2_DIV2;
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RCC->D3CFGR = RCC_D3CFGR_D3PPRE_DIV2;
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// Switch on PLL1
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RCC->CR = rcc_cr = rcc_cr | RCC_CR_PLL1ON;
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while (!(RCC->CR & RCC_CR_PLL1RDY))
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;
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// Switch system clock source (SYSCLK) to PLL1
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RCC->CFGR = RCC_CFGR_SW_PLL1;
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL1)
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;
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// Set the source of FDCAN clock to pll1_q_ck
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RCC->D2CCIP1R = 1 << RCC_D2CCIP1R_FDCANSEL_Pos;
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// Configure USB to use HSI48 clock
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if (CONFIG_USB) {
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RCC->CR = rcc_cr = rcc_cr | RCC_CR_HSI48ON;
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while ((RCC->CR & RCC_CR_HSI48RDY) == 0)
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;
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enable_pclock((uint32_t)CRS);
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CRS->CFGR &= ~CRS_CFGR_SYNCSRC;
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CRS->CR = (CRS->CR & CRS_CR_TRIM) | CRS_CR_CEN | CRS_CR_AUTOTRIMEN;
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RCC->D2CCIP2R = RCC_D2CCIP2R_USBSEL;
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}
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}
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/****************************************************************
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* Bootloader
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****************************************************************/
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// Handle reboot requests
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void
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bootloader_request(void)
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{
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try_request_canboot();
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dfu_reboot();
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}
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/****************************************************************
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* Startup
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****************************************************************/
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// Main entry point - called from armcm_boot.c:ResetHandler()
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void
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armcm_main(void)
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{
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// Run SystemInit() and then restore VTOR
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SystemInit();
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RCC->D1CCIPR = 0x00000000;
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RCC->D2CCIP1R = 0x00000000;
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RCC->D2CCIP2R = 0x00000000;
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RCC->D3CCIPR = 0x00000000;
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RCC->APB1LENR = 0x00000000;
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RCC->APB1HENR = 0x00000000;
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RCC->APB2ENR = 0x00000000;
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RCC->APB3ENR = 0x00000000;
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RCC->APB4ENR = 0x00000000;
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RCC->AHB1ENR = 0x00000000;
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SCB->VTOR = (uint32_t)VectorTable;
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dfu_reboot_check();
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clock_setup();
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sched_main();
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}
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