docs: Note version 0.3.0 release

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>

.gitignore

@@ -0,0 +1,5 @@
+out
+*.so
+*.pyc
+.config
+.config.old

COPYING

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+  16. Limitation of Liability.
+
+  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
+THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+  17. Interpretation of Sections 15 and 16.
+
+  If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+    <program>  Copyright (C) <year>  <name of author>
+    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.

Makefile

@@ -0,0 +1,126 @@
+# Klipper build system
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+
+# Output directory
+OUT=out/
+
+# Kconfig includes
+export HOSTCC             := $(CC)
+export CONFIG_SHELL       := sh
+export KCONFIG_AUTOHEADER := autoconf.h
+export KCONFIG_CONFIG     := $(CURDIR)/.config
+-include $(KCONFIG_CONFIG)
+
+# Common command definitions
+CC=$(CROSS_PREFIX)gcc
+AS=$(CROSS_PREFIX)as
+LD=$(CROSS_PREFIX)ld
+OBJCOPY=$(CROSS_PREFIX)objcopy
+OBJDUMP=$(CROSS_PREFIX)objdump
+STRIP=$(CROSS_PREFIX)strip
+CPP=cpp
+PYTHON=python
+
+# Source files
+src-y =
+dirs-y = src
+
+# Default compiler flags
+cc-option=$(shell if test -z "`$(1) $(2) -S -o /dev/null -xc /dev/null 2>&1`" \
+    ; then echo "$(2)"; else echo "$(3)"; fi ;)
+
+CFLAGS-y := -I$(OUT) -Isrc -I$(OUT)board-generic/ -O2 -MD -g \
+    -Wall -Wold-style-definition $(call cc-option,$(CC),-Wtype-limits,) \
+    -ffunction-sections -fdata-sections
+CFLAGS-y += -flto -fwhole-program -fno-use-linker-plugin
+
+LDFLAGS-y := -Wl,--gc-sections -fno-whole-program
+
+CPPFLAGS = -I$(OUT) -P -MD -MT $@
+
+CFLAGS = $(CFLAGS-y)
+LDFLAGS = $(LDFLAGS-y)
+
+# Default targets
+target-y := $(OUT)klipper.elf
+
+all:
+
+# Run with "make V=1" to see the actual compile commands
+ifdef V
+Q=
+else
+Q=@
+MAKEFLAGS += --no-print-directory
+endif
+
+# Include board specific makefile
+include src/Makefile
+-include src/$(patsubst "%",%,$(CONFIG_BOARD_DIRECTORY))/Makefile
+
+################ Common build rules
+
+$(OUT)%.o: %.c $(OUT)autoconf.h $(OUT)board-link
+	@echo "  Compiling $@"
+	$(Q)$(CC) $(CFLAGS) -c $< -o $@
+
+################ Main build rules
+
+$(OUT)board-link: $(KCONFIG_CONFIG)
+	@echo "  Creating symbolic link $(OUT)board"
+	$(Q)mkdir -p $(addprefix $(OUT), $(dirs-y))
+	$(Q)touch $@
+	$(Q)ln -Tsf $(PWD)/src/$(CONFIG_BOARD_DIRECTORY) $(OUT)board
+	$(Q)mkdir -p $(OUT)board-generic
+	$(Q)ln -Tsf $(PWD)/src/generic $(OUT)board-generic/board
+
+$(OUT)declfunc.lds: src/declfunc.lds.S
+	@echo "  Precompiling $@"
+	$(Q)$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ $< -o $@
+
+$(OUT)klipper.o: $(patsubst %.c, $(OUT)src/%.o,$(src-y)) $(OUT)declfunc.lds
+	@echo "  Linking $@"
+	$(Q)$(CC) $(CFLAGS) -Wl,-r -Wl,-T,$(OUT)declfunc.lds -nostdlib $(patsubst %.c, $(OUT)src/%.o,$(src-y)) -o $@
+
+$(OUT)compile_time_request.o: $(OUT)klipper.o ./scripts/buildcommands.py
+	@echo "  Building $@"
+	$(Q)$(OBJCOPY) -j '.compile_time_request' -O binary $< $(OUT)klipper.o.compile_time_request
+	$(Q)$(PYTHON) ./scripts/buildcommands.py -d $(OUT)klipper.dict $(OUT)klipper.o.compile_time_request $(OUT)compile_time_request.c
+	$(Q)$(CC) $(CFLAGS) -c $(OUT)compile_time_request.c -o $@
+
+$(OUT)klipper.elf: $(OUT)klipper.o $(OUT)compile_time_request.o
+	@echo "  Linking $@"
+	$(Q)$(CC) $(CFLAGS) $(LDFLAGS) $^ -o $@
+
+################ Kconfig rules
+
+define do-kconfig
+$(Q)mkdir -p $(OUT)/scripts/kconfig/lxdialog
+$(Q)mkdir -p $(OUT)/include/config
+$(Q)$(MAKE) -C $(OUT) -f $(CURDIR)/scripts/kconfig/Makefile srctree=$(CURDIR) src=scripts/kconfig obj=scripts/kconfig Q=$(Q) Kconfig=$(CURDIR)/src/Kconfig $1
+endef
+
+$(OUT)autoconf.h : $(KCONFIG_CONFIG) ; $(call do-kconfig, silentoldconfig)
+$(KCONFIG_CONFIG): src/Kconfig ; $(call do-kconfig, olddefconfig)
+%onfig: ; $(call do-kconfig, $@)
+help: ; $(call do-kconfig, $@)
+
+
+################ Generic rules
+
+# Make definitions
+.PHONY : all clean distclean FORCE
+.DELETE_ON_ERROR:
+
+all: $(target-y)
+
+clean:
+	$(Q)rm -rf $(OUT)
+
+distclean: clean
+	$(Q)rm -f .config .config.old
+
+-include $(OUT)*.d $(patsubst %,$(OUT)%/*.d,$(dirs-y))

README.md

@@ -0,0 +1,29 @@
+Welcome to the Klipper project!
+
+This project implements a 3d-printer firmware. There are two parts to
+this firmware - code that runs on a micro-controller and code that
+runs on a host machine. The host software does the work to build a
+schedule of events, while the micro-controller software does the work
+to execute the provided schedule at the specified times.
+
+See the [features](docs/Features.md) document to find out why you
+should use Klipper. To begin using Klipper start by
+[installing](docs/Installation.md) it.
+
+There is also [developer documentation](docs/Overview.md) available.
+
+License
+=======
+
+Klipper is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 3 of the License, or
+(at your option) any later version.
+
+Klipper is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with Klipper.  If not, see <http://www.gnu.org/licenses/>.

config/avrsim.cfg

@@ -0,0 +1,80 @@
+# Support for internal testing with the "simulavr" program.  To use
+# this config, compile the firmware for an AVR atmega644p, disable the
+# AVR watchdog timer, set the MCU frequency to 20000000, and set the
+# serial baud rate to 115200.
+
+[stepper_x]
+# Pins: PA5, PA4, PA1
+step_pin: ar29
+dir_pin: ar28
+enable_pin: ar25
+step_distance: .0225
+endstop_pin: ^ar0
+position_min: -0.25
+position_endstop: 0
+position_max: 200
+
+[stepper_y]
+# Pins: PA3, PA2
+step_pin: ar27
+dir_pin: ar26
+enable_pin: ar25
+step_distance: .0225
+endstop_pin: ^ar1
+position_min: -0.25
+position_endstop: 0
+position_max: 200
+
+[stepper_z]
+# Pins: PC7, PC6
+step_pin: ar23
+dir_pin: ar22
+enable_pin: ar25
+step_distance: .005
+endstop_pin: ^ar2
+position_min: 0.1
+position_endstop: 0.5
+position_max: 200
+
+[extruder]
+# Pins: PC3, PC2
+step_pin: ar19
+dir_pin: ar18
+enable_pin: ar25
+step_distance: .004242
+max_velocity: 200000
+max_accel: 3000
+heater_pin: ar4
+thermistor_pin: analog1
+thermistor_type: EPCOS 100K B57560G104F
+control: pid
+pid_Kp: 22.2
+pid_Ki: 1.08
+pid_Kd: 114
+min_temp: 0
+min_extrude_temp: 0
+max_temp: 210
+
+[heater_bed]
+heater_pin: ar3
+thermistor_pin: analog0
+thermistor_type: EPCOS 100K B57560G104F
+control: watermark
+min_temp: 0
+max_temp: 110
+
+[fan]
+pin: ar14
+hard_pwm: 1
+
+[mcu]
+serial: /tmp/pseudoserial
+baud: 250000
+pin_map: arduino
+
+[printer]
+kinematics: cartesian
+max_velocity: 500
+max_accel: 3000
+max_z_velocity: 250
+max_z_accel: 30

config/example-delta.cfg

@@ -0,0 +1,95 @@
+# This file serves as documentation for config parameters of delta
+# style printers. One may copy and edit this file to configure a new
+# delta printer. Only parameters unique to delta printers are
+# described here - see the "example.cfg" file for description of
+# common config parameters.
+
+# DO NOT COPY THIS FILE WITHOUT CAREFULLY READING AND UPDATING IT
+# FIRST. Incorrectly configured parameters may cause damage.
+
+# The stepper_a section describes the stepper controlling the front
+# left tower (at 210 degrees). This section also controls the homing
+# parameters (homing_speed, homing_retract_dist) and maximum tower
+# length (position_max) for all towers.
+[stepper_a]
+step_pin: ar54
+dir_pin: ar55
+enable_pin: !ar38
+step_distance: .01
+endstop_pin: ^ar2
+homing_speed: 50.0
+position_endstop: 297.05
+position_max: 297.55
+
+# The stepper_b section describes the stepper controlling the front
+# right tower (at 330 degrees)
+[stepper_b]
+step_pin: ar60
+dir_pin: ar61
+enable_pin: !ar56
+step_distance: .01
+endstop_pin: ^ar15
+position_endstop: 297.05
+
+# The stepper_c section describes the stepper controlling the rear
+# tower (at 90 degrees)
+[stepper_c]
+step_pin: ar46
+dir_pin: ar48
+enable_pin: !ar62
+step_distance: .01
+endstop_pin: ^ar19
+position_endstop: 297.05
+
+[extruder]
+step_pin: ar26
+dir_pin: ar28
+enable_pin: !ar24
+step_distance: .0022
+max_velocity: 200
+max_accel: 3000
+heater_pin: ar10
+thermistor_pin: analog13
+thermistor_type: ATC Semitec 104GT-2
+control: pid
+pid_Kp: 22.2
+pid_Ki: 1.08
+pid_Kd: 114
+min_temp: 0
+max_temp: 250
+
+[heater_bed]
+heater_pin: ar8
+thermistor_pin: analog14
+thermistor_type: EPCOS 100K B57560G104F
+control: watermark
+min_temp: 0
+max_temp: 130
+
+# Extruder print fan (omit section if fan not present)
+#[fan]
+#pin: ar9
+#hard_pwm: 1
+
+[mcu]
+serial: /dev/ttyACM0
+baud: 250000
+pin_map: arduino
+
+[printer]
+kinematics: delta
+#   This option must be "delta" for linear delta printers
+max_velocity: 300
+max_accel: 3000
+max_z_velocity: 200
+#   For delta printers this limits the maximum velocity (in mm/s) of
+#   moves with z axis movement. This setting can be used to reduce the
+#   maximum speed of up/down moves (which require a higher step rate
+#   than other moves on a delta printer).
+delta_arm_length: 333.0
+#   Length (in mm) of the diagonal rods that connect the linear axes
+#   to the print head
+delta_radius: 174.75
+#   Radius (in mm) of the horizontal circle formed by the three linear
+#   axis towers. This parameter may also be calculated as:
+#    delta_radius = smooth_rod_offset - effector_offset - carriage_offset

config/example.cfg

@@ -0,0 +1,211 @@
+# This file serves as documentation for config parameters. One may
+# copy and edit this file to configure a new cartesian style
+# printer. For delta style printers, see the "example-delta.cfg" file.
+
+# DO NOT COPY THIS FILE WITHOUT CAREFULLY READING AND UPDATING IT
+# FIRST. Incorrectly configured parameters may cause damage.
+
+# A note on pin names: pins may be configured with a hardware name
+# (such as "PA4") or with an Arduino alias name (such as "ar29" or
+# "analog3"). In order to use Arduino names, the pin_map variable in
+# the mcu section must be present and have a value of "arduino".
+# Pin names may be preceded by an '!' to indicate that a reverse
+# polarity should be used (eg, trigger on low instead of high). Input
+# pins may be preceded by a '^' to indicate that a hardware pull-up
+# resistor should be enabled for the pin.
+
+
+# The stepper_x section is used to describe the stepper controlling
+# the X axis in a cartesian robot
+[stepper_x]
+step_pin: ar29
+#   Step GPIO pin (triggered high)
+dir_pin: !ar28
+#   Direction GPIO pin (high indicates positive direction)
+enable_pin: !ar25
+#   Enable pin (default is enable high; use ! to indicate enable low)
+step_distance: .0225
+#   Distance in mm that each step causes the axis to travel
+endstop_pin: ^ar0
+#   Endstop switch detection pin
+homing_speed: 50.0
+#   Maximum velocity (in mm/s) of the stepper when homing
+homing_retract_dist: 5.0
+#   Distance to backoff (in mm) before homing a second time during homing
+homing_positive_dir: False
+#   If true, homes in a positive direction (away from zero)
+homing_stepper_phases: 0
+#   One may optionally set this to the number of phases of the stepper
+#   motor driver (which is the number of micro-steps multiplied by
+#   four). When set, the phase of the stepper driver will be used
+#   during homing to improve the accuracy of the endstop switch.
+homing_endstop_accuracy: 0.200
+#   Sets the expected accuracy (in mm) of the endstop. This represents
+#   the maximum error distance the endstop may trigger (eg, if an
+#   endstop may occasionally trigger 100um early or up to 100um late
+#   then set this to 0.200 for 200um). This setting is used with
+#   homing_stepper_phases and is only useful if that parameter is also
+#   configured.
+#homing_endstop_phase: 0
+#   This specifies the phase of the stepper motor driver to expect
+#   when hitting the endstop. This setting is only meaningful if
+#   homing_stepper_phases is also set. Only set this value if one is
+#   sure the stepper motor driver is reset every time the mcu is
+#   reset. If this is not set, but homing_stepper_phases is set, then
+#   the stepper phase will be detected on the first home and that
+#   phase will be used on all subsequent homes.
+position_min: -0.25
+#   Minimum valid distance (in mm) the user may command the stepper to
+#   move to
+position_endstop: 0
+#   Location of the endstop (in mm)
+position_max: 200
+#   Maximum valid distance (in mm) the user may command the stepper to
+#   move to
+
+# The stepper_y section is used to describe the stepper controlling
+# the Y axis in a cartesian robot. It has the same settings as the
+# stepper_x section
+[stepper_y]
+step_pin: ar27
+dir_pin: ar26
+enable_pin: !ar25
+step_distance: .0225
+endstop_pin: ^ar1
+position_min: -0.25
+position_endstop: 0
+position_max: 200
+
+# The stepper_z section is used to describe the stepper controlling
+# the Z axis in a cartesian robot. It has the same settings as the
+# stepper_x section
+[stepper_z]
+step_pin: ar23
+dir_pin: !ar22
+enable_pin: !ar25
+step_distance: .005
+endstop_pin: ^ar2
+position_min: 0.1
+position_endstop: 0.5
+position_max: 200
+
+# The extruder section is used to describe both the stepper
+# controlling the printer extruder and the heater parameters for the
+# nozzle. The stepper configuration has the same settings as the
+# stepper_x section and the heater configuration has the same settings
+# as the heater_bed section
+[extruder]
+step_pin: ar19
+dir_pin: ar18
+enable_pin: !ar25
+step_distance: .004242
+max_velocity: 200000
+#   Maximum velocity (in mm/s) of the extruder motor for extrude only
+#   moves.
+max_accel: 3000
+#   Maximum acceleration (in mm/s^2) of the extruder motor for extrude
+#   only moves.
+#
+# The remaining variables describe the extruder heater
+pressure_advance: 0.0
+#   The amount of raw filament to push into the extruder during
+#   extruder acceleration. An equal amount of filament is retracted
+#   during deceleration. It is measured in millimeters per
+#   millimeter/second
+heater_pin: ar4
+#   PWM output pin controlling the heater
+thermistor_pin: analog1
+#   Analog input pin connected to thermistor
+thermistor_type: EPCOS 100K B57560G104F
+#   Type of thermistor (see klippy/heater.py for available types)
+pullup_resistor: 4700
+#   The resistance (in ohms) of the pullup attached to the thermistor
+control: pid
+#   Control algorithm (either pid or watermark)
+pid_Kp: 22.2
+#   Kp is the "proportional" constant for the pid
+pid_Ki: 1.08
+#   Ki is the "integral" constant for the pid
+pid_Kd: 114
+#   Kd is the "derivative" constant for the pid
+pid_deriv_time: 2.0
+#   A time value (in seconds) over which the derivative in the pid
+#   will be smoothed to reduce the impact of measurement noise
+pid_integral_max: 255
+#   The maximum "windup" the integral term may accumulate
+min_extrude_temp: 170
+#   The minimum temperature (in Celsius) at which extruder move
+#   commands may be issued
+min_temp: 0
+#   Minimum temperature in Celsius (mcu will shutdown if not met)
+max_temp: 210
+#   Maximum temperature (mcu will shutdown if temperature is above
+#   this value)
+
+# The heater_bed section describes a heated bed (if present - omit
+# section if not present).
+[heater_bed]
+heater_pin: ar3
+thermistor_pin: analog0
+thermistor_type: EPCOS 100K B57560G104F
+control: watermark
+max_delta: 2.0
+#   The number of degrees in Celsius above the target temperature
+#   before disabling the heater as well as the number of degrees below
+#   the target before re-enabling the heater.
+min_temp: 0
+max_temp: 110
+
+# Extruder print fan (omit section if fan not present)
+[fan]
+pin: ar14
+#   PWM output pin controlling the heater
+hard_pwm: 1
+#   Set this value to force hardware PWM instead of software PWM. Set
+#   to 1 to force a hardware PWM at the fastest rate; set to a higher
+#   number (eg, 1024) to force hardware PWM with the given cycle time
+#   in clock ticks.
+kick_start_time: 0.100
+#   Time (in seconds) to run the fan at full speed when first enabling
+#   it (helps get the fan spinning)
+
+# Micro-controller information
+[mcu]
+serial: /dev/ttyACM0
+#   The serial port to connect to the MCU
+baud: 250000
+#   The baud rate to use
+pin_map: arduino
+#   This option may be used to enable Arduino pin name aliases
+custom:
+#   This option may be used to specify a set of custom
+#   micro-controller commands to be sent at the start of the
+#   connection. It may be used to configure the initial settings of
+#   LEDs, to configure micro-stepping pins, to configure a digipot,
+#   etc.
+
+# The printer section controls high level printer settings
+[printer]
+kinematics: cartesian
+#   This option must be "cartesian" for cartesian printers
+max_velocity: 500
+#   Maximum velocity (in mm/s) of the toolhead (relative to the
+#   print)
+max_accel: 3000
+#   Maximum acceleration (in mm/s^2) of the toolhead (relative to the
+#   print)
+max_z_velocity: 250
+#   For cartesian printers this sets the maximum velocity (in mm/s) of
+#   movement along the z axis. This setting can be used to restrict
+#   the maximum speed of the z stepper motor on cartesian printers.
+max_z_accel: 30
+#   For cartesian printers this sets the maximum acceleration (in
+#   mm/s^2) of movement along the z axis. It limits the acceleration
+#   of the z stepper motor on cartesian printers.
+motor_off_time: 60
+#   Time (in seconds) of idle time before the printer will try to
+#   disable active motors.
+junction_deviation: 0.02
+#   Distance (in mm) used to control the internal approximated
+#   centripetal velocity cornering algorithm. A larger number will
+#   permit higher "cornering speeds" at the junction of two moves.

config/makergear-m2-2012.cfg

@@ -0,0 +1,106 @@
+# Support for Makergear M2 printers circa 2012 that have the RAMBo
+# v1.0d electronics along with the V3A extruder.  The electronics use
+# Allegro A4984 stepper drivers with 1/8th micro-stepping.  To use
+# this config, the firmware should be compiled for the AVR atmega2560.
+
+[stepper_x]
+step_pin: PC0
+dir_pin: !PL1
+enable_pin: !PA7
+step_distance: .0225
+endstop_pin: ^!PB6
+homing_speed: 50.0
+homing_stepper_phases: 32
+homing_endstop_accuracy: .200
+position_min: -0.25
+position_endstop: 0.0
+position_max: 200
+
+[stepper_y]
+step_pin: PC1
+dir_pin: PL0
+enable_pin: !PA6
+step_distance: .0225
+endstop_pin: ^!PB5
+homing_speed: 50.0
+homing_stepper_phases: 32
+homing_endstop_accuracy: .200
+position_min: -0.25
+position_endstop: 0.0
+position_max: 250
+
+[stepper_z]
+step_pin: PC2
+dir_pin: !PL2
+enable_pin: !PA5
+step_distance: .005
+endstop_pin: ^!PB4
+homing_speed: 4.0
+homing_retract_dist: 2.0
+homing_stepper_phases: 32
+homing_endstop_accuracy: .050
+position_min: 0.1
+position_endstop: 0.7
+position_max: 200
+
+[extruder]
+step_pin: PC3
+dir_pin: PL6
+enable_pin: !PA4
+step_distance: .004242
+max_velocity: 200000
+max_accel: 3000
+pressure_advance: 0.07
+heater_pin: PH6
+thermistor_pin: PF0
+thermistor_type: EPCOS 100K B57560G104F
+control: pid
+pid_Kp: 7.0
+pid_Ki: 0.1
+pid_Kd: 12
+min_temp: 0
+max_temp: 210
+
+[heater_bed]
+heater_pin: PE5
+thermistor_pin: PF2
+thermistor_type: EPCOS 100K B57560G104F
+control: watermark
+min_temp: 0
+max_temp: 100
+
+[fan]
+pin: PH5
+hard_pwm: 1
+
+[mcu]
+serial: /dev/ttyACM0
+baud: 250000
+custom:
+  # Nozzle fan
+  set_pwm_out pin=PH3 cycle_ticks=1 value=155
+  # Turn off yellow led
+  set_digital_out pin=PB7 value=0
+  # Stepper micro-step pins
+  set_digital_out pin=PG1 value=1
+  set_digital_out pin=PG0 value=1
+  set_digital_out pin=PK7 value=1
+  set_digital_out pin=PG2 value=1
+  set_digital_out pin=PK6 value=1
+  set_digital_out pin=PK5 value=1
+  set_digital_out pin=PK3 value=1
+  set_digital_out pin=PK4 value=1
+  # Initialize digipot
+  send_spi_message pin=PD7 msg=0487 # X = ~0.75A
+  send_spi_message pin=PD7 msg=0587 # Y = ~0.75A
+  send_spi_message pin=PD7 msg=0387 # Z = ~0.75A
+  send_spi_message pin=PD7 msg=00A5 # E0
+  send_spi_message pin=PD7 msg=017D # E1
+
+[printer]
+kinematics: cartesian
+max_velocity: 500
+max_accel: 3000
+max_z_velocity: 250
+max_z_accel: 30
+motor_off_time: 600

docs/Code_Overview.md

@@ -0,0 +1,108 @@
+This document describes the overall code layout and major code flow of
+Klipper.
+
+Directory Layout
+================
+
+The **src/** directory contains the C source for the micro-controller
+code. The **src/avr/** directory contains specific code for Atmel
+ATmega micro-controllers. The **src/sam3x8e/** directory contains code
+specific to the Arduino Due style ARM micro-controllers. The
+**src/simulator/** contains code stubs that allow the micro-controller
+to be test compiled on other architectures. The **src/generic/**
+directory contains helper code that may be useful across different
+host architectures. The build arranges for includes of
+"board/somefile.h" to first look in the current architecture directory
+(eg, src/avr/somefile.h) and then in the generic directory (eg,
+src/generic/somefile.h).
+
+The **klippy/** directory contains the C and Python source for the
+host part of the firmware.
+
+The **lib/** directory contains external 3rd-party library code that
+is necessary to build some targets.
+
+The **config/** directory contains example printer configuration
+files.
+
+The **scripts/** directory contains build-time scripts useful for
+compiling the micro-controller code.
+
+During compilation, the build may create an **out/** directory. This
+contains temporary build time objects. The final micro-controller
+object that is built is **out/klipper.elf.hex** on AVR and
+**out/klipper.bin** on ARM.
+
+Micro-controller code flow
+==========================
+
+Execution of the micro-controller code starts in architecture specific
+code (eg, **src/avr/main.c**) which ultimately calls sched_main()
+located in **src/sched.c**. The sched_main() code starts by running
+all functions that have been tagged with the DECL_INIT() macro. It
+then goes on to repeatedly run all functions tagged with the
+DECL_TASK() macro.
+
+One of the main task functions is command_task() located in
+**src/command.c**. This function processes incoming serial commands
+and runs the associated command function for them. Command functions
+are declared using the DECL_COMMAND() macro.
+
+Task, init, and command functions always run with interrupts enabled
+(however, they can temporarily disable interrupts if needed). These
+functions should never pause, delay, or do any work that lasts more
+than a few micro-seconds. These functions schedule work at specific
+times by scheduling timers.
+
+Timer functions are scheduled by calling sched_timer() (located in
+**src/sched.c**). The scheduler code will arrange for the given
+function to be called at the requested clock time. Timer interrupts
+are initially handled in an architecture specific interrupt handler
+(eg, **src/avr/timer.c**), but this just calls sched_timer_kick()
+located in **src/sched.c**. The timer interrupt leads to execution of
+schedule timer functions.  Timer functions always run with interrupts
+disabled. The timer functions should always complete within a few
+micro-seconds. At completion of the timer event, the function may
+choose to reschedule itself.
+
+In the event an error is detected the code can invoke shutdown() (a
+macro which calls sched_shutdown() located in **src/sched.c**).
+Invoking shutdown() causes all functions tagged with the
+DECL_SHUTDOWN() macro to be run. Shutdown functions always run with
+interrupts disabled.
+
+Much of the functionality of the micro-controller involves working
+with General-Purpose Input/Output pins (GPIO). In order to abstract
+the low-level architecture specific code from the high-level task
+code, all GPIO events are implemented in architectures specific
+wrappers (eg, **src/avr/gpio.c**). The code is compiled with gcc's
+"-flto -fwhole-program" optimization which does an excellent job of
+inlining functions across compilation units, so most of these tiny
+gpio functions are inlined into their callers, and there is no
+run-time cost to using them.
+
+Klippy code overview
+====================
+
+The host code (Klippy) is intended to run on a low-cost computer (such
+as a Raspberry Pi) paired with the micro-controller. The code is
+primarily written in Python, however it does use CFFI to implement
+some functionality in C code.
+
+Initial execution starts in **klippy/klippy.py**. This reads the
+command-line arguments, opens the printer config file, instantiates
+the main printer objects, and starts the serial connection. The main
+execution of gcode commands is in the process_commands() method in
+**klippy/gcode.py**. This code translates the gcode commands into
+printer object calls, which frequently translate the actions to
+commands to be executed on the micro-controller (as declared via the
+DECL_COMMAND macro in the micro-controller code).
+
+There are four threads in the Klippy host code. The main thread
+handles incoming gcode commands. A second thread (which resides
+entirely in the **klippy/serialqueue.c** C code) handles low-level IO
+with the serial port. The third thread is used to process response
+messages from the micro-controller in the Python code (see
+**klippy/serialhdl.py**). The fourth thread writes debug messages to
+the log (see **klippy/queuelogger.py**) so that the other threads
+never block on log writes.

docs/Debugging.md

@@ -0,0 +1,131 @@
+The Klippy host code has some tools to help in debugging the firmware.
+
+Translating gcode files to firmware commands
+============================================
+
+The Klippy host code can run in a batch mode to produce the low-level
+firmware commands associated with a gcode file. Inspecting these
+low-level firmware commands is useful when trying to understand the
+actions of the low-level hardware. It can also be useful to compare
+the difference in firmware commands after a code change.
+
+To run Klippy in this batch mode, there is a one time step necessary
+to generate the firmware "data dictionary". This is done by compiling
+the firmware code to obtain the **out/klipper.dict** file:
+
+```
+make menuconfig
+make
+```
+
+Once the above is done it is possible to run Klipper in batch mode
+(see [installation](Installation.md) for the steps necessary to build
+the python virtual environment and a printer.cfg file):
+
+```
+~/klippy-env/bin/python ./klippy/klippy.py ~/printer.cfg -i test.gcode -o test.serial -v -d out/klipper.dict
+```
+
+The above will produce a file **test.serial** with the binary serial
+output. This output can be translated to readable text with:
+
+```
+~/klippy-env/bin/python ./klippy/parsedump.py out/klipper.dict test.serial > test.txt
+```
+
+The resulting file **test.txt** contains a human readable list of
+firmware commands.
+
+The batch mode disables certain response / request commands in order
+to function. As a result, there will be some differences between
+actual firmware commands and the above output. The generated data is
+useful for testing and inspection; it is not useful for sending to a
+real micro-controller.
+
+Testing with simulavr
+=====================
+
+The [simulavr](http://www.nongnu.org/simulavr/) tool enables one to
+simulate an Atmel ATmega micro-controller. This section describes how
+one can run test gcode files through simulavr. It is recommended to
+run this on a desktop class machine (not a Raspberry Pi) as it does
+require significant cpu to run efficiently.
+
+To use simulavr, download the simulavr package and compile with python
+support:
+
+```
+git clone git://git.savannah.nongnu.org/simulavr.git
+cd simulavr
+./bootstrap
+./configure --enable-python
+make
+```
+
+Note that the build system may need to have some packages (such as
+swig) installed in order to build the python module. Make sure the
+file **src/python/_pysimulavr.so** is present after the above
+compilation.
+
+To compile Klipper for use in simulavr, run:
+
+```
+cd /patch/to/klipper
+make menuconfig
+```
+
+and compile the firmware for an AVR atmega644p, disable the AVR
+watchdog timer, and set the MCU frequency to 20000000. Then one can
+compile Klipper (run `make`) and then start the simulation with:
+
+```
+PYTHONPATH=/path/to/simulavr/src/python/ ./scripts/avrsim.py -m atmega644 -s 20000000 -b 250000 out/klipper.elf
+```
+
+It may be necessary to create a python virtual environment to run
+Klippy on the target machine. To do so, run:
+
+```
+virtualenv ~/klippy-env
+~/klippy-env/bin/pip install cffi==1.6.0 pyserial==2.7
+```
+
+Then, with simulavr running in another window, one can run the
+following to read gcode from a file (eg, "test.gcode"), process it
+with Klippy, and send it to Klipper running in simulavr:
+
+```
+~/klippy-env/bin/python ./klippy/klippy.py config/avrsim.cfg -i test.gcode -v
+```
+
+Using simulavr with gtkwave
+---------------------------
+
+One useful feature of simulavr is its ability to create signal wave
+generation files with the exact timing of events. To do this, follow
+the directions above, but run avrsim.py with a command-line like the
+following:
+
+```
+PYTHONPATH=/path/to/simulavr/src/python/ ./scripts/avrsim.py -m atmega644 -s 20000000 -b 250000 out/klipper.elf -t PORTA.PORT,PORTC.PORT
+```
+
+The above would create a file **avrsim.vcd** with information on each
+change to the GPIOs on PORTA and PORTB. This could then be viewed
+using gtkwave with:
+
+```
+gtkwave avrsim.vcd
+```
+
+Manually sending commands to the micro-controller
+-------------------------------------------------
+
+Normally, Klippy would be used to translate gcode commands to Klipper
+commands. However, it's also possible to manually send Klipper
+commands (functions marked with the DECL_COMMAND() macro in the
+Klipper source code). To do so, run:
+
+```
+~/klippy-env/bin/python ./klippy/console.py /tmp/pseudoserial 250000
+```

docs/Features.md

@@ -0,0 +1,85 @@
+Klipper is an experimental 3d printer firmware. It has several
+compelling features:
+
+* High precision stepper movement. Klipper utilizes an application
+  processor (such as a low-cost Raspberry Pi) when calculating printer
+  movements. The application processor determines when to step each
+  stepper motor, it compresses those events, transmits them to the
+  micro-controller, and then the micro-controller executes each event
+  at the requested time.  Each stepper event is scheduled with a
+  precision of no less than 50 micro-seconds. The software does not
+  use kinematic estimations (such as the Bresenham algorithm) -
+  instead it calculates precise step times based on the physics of
+  acceleration and the physics of the machine kinematics. More precise
+  stepper movement translates to quieter and more stable printer
+  operation.
+
+* Best in class performance. Klipper is able to achieve high stepping
+  rates on both new and old micro-controllers. Even an old 8bit AVR
+  micro-controller can obtain rates up to 150K steps per second. On
+  more recent ARM micro-controllers, rates over 350K steps per second
+  are possible. Higher stepper rates enable higher print
+  velocities. The stepper event timing remains precise even at high
+  speeds which improves overall stability.
+
+* Configuration via simple config file. There's no need to reflash the
+  micro-controller to change a setting. All of Klipper's configuration
+  is stored in a standard config file which can be easily edited. This
+  makes it easier to setup and maintain the hardware.
+
+* Portable code. Klipper works on both ARM and AVR
+  micro-controllers. Existing "reprap" style printers can run Klipper
+  without hardware modification - just add a Raspberry Pi. Klipper's
+  internal code layout makes it easier to support other
+  micro-controller architectures as well.
+
+* Simpler code. Klipper uses a very high level language (Python) for
+  most code. The kinematics algorithms, the gcode parsing, the heating
+  and thermistor algorithms, etc. are all written in Python. This
+  makes it easier to develop new functionality.
+
+* Advanced features. Klipper implements the "pressure advance"
+  algorithm for extruders. When properly tuned, pressure advance
+  reduces extruder ooze. Klipper also implements a novel "stepper
+  phase endstop" algorithm that can dramatically improve the accuracy
+  of typical endstop switches. When properly tuned it can improve a
+  print's first layer bed adhesion.
+
+To get started with Klipper, read the [installation](Installation.md)
+guide.
+
+Common features supported by Klipper
+====================================
+
+Klipper supports many standard 3d printer features:
+
+* Works with Octoprint. This allows the printer to be controlled using
+  a regular web-browser. The same Raspberry Pi that runs Klipper can
+  also run Octoprint.
+
+* Standard G-Code support. Common g-code commands that are produced by
+  typical "slicers" are supported. One may continue to use Slic3r,
+  Cura, etc. with Klipper.
+
+* Constant speed acceleration support. All printer moves will
+  gradually accelerate from standstill to cruising speed and then
+  decelerate back to a standstill.
+
+* "Lookahead" support. The incoming stream of G-Code movement commands
+  are queued and analyzed - the acceleration between movements in a
+  similar direction will be optimized to reduce print stalls and
+  improve overall print time.
+
+* Support for both delta printers and cartesian style printers.
+
+Step Benchmarks
+===============
+
+Below are the results of stepper performance tests. The numbers shown
+represent total number of steps per second on the micro-controller.
+
+| Micro-controller  | 1 stepper active | 3 steppers active |
+| ----------------- | ---------------- | ----------------- |
+| 20Mhz AVR         | 158.7K           | 103K              |
+| 16Mhz AVR         | 126.9K           | 82K               |
+| Arduino Due (ARM) | 352.9K           | 288K              |

docs/Firmware_Commands.md

@@ -0,0 +1,278 @@
+This document provides high-level information on common firmware
+commands. It is not an authoritative reference for these commands, nor
+is it an exclusive list of all available firmware commands.
+
+This document may be useful for users needing to configure a set of
+hardware actions that their printer may require at startup (via the
+"custom" field in the printer config file), and it may be useful for
+developers wishing to obtain a high-level feel for available firmware
+commands.
+
+See the [protocol](Protocol.md) document for more information on the
+format of commands and their low-level transmission. The commands here
+are described using their "printf" style syntax - for those unfamiliar
+with that format, just note that where a '%...' sequence is seen it
+should be replaced with an actual integer.
+
+Startup Commands
+================
+
+It may be necessary to take certain one-time actions to configure the
+micro-controller and its peripherals. This section lists common
+commands available for that purpose. Unlike other firmware commands,
+these commands run as soon as they are received by the firmware and
+they do not require any particular setup.
+
+These commands are most useful in the "custom" block of the "mcu"
+section of the printer configuration file. This feature is typically
+used to configure the initial settings of LEDs, to configure
+micro-stepping pins, to configure a digipot, etc.
+
+Several of these commands will take a "pin=%u" parameter. The
+low-level firmware uses integer encodings of the hardware pin numbers,
+but to make things more readable the host will translate human
+readable pin names (eg, "PA3") to their equivalent integer
+encodings. By convention, any parameter named "pin" or that has a
+"_pin" suffix will use pin name translation by the host.
+
+Common startup commands:
+
+* set_digital_out pin=%u value=%c : This command immediately
+  configures the given pin as a digital out GPIO and it sets it to
+  either a low level (value=0) or a high level (value=1). This command
+  may be useful for configuring the initial value of LEDs and for
+  configuring the initial value of stepper driver micro-stepping pins.
+
+* set_pwm_out pin=%u cycle_ticks=%u value=%c : This command will
+  immediately configure the given pin to use hardware based
+  pulse-width-modulation (PWM) with the given number of
+  cycle_ticks. The "cycle_ticks" is the number of MCU clock ticks each
+  power on and power off cycle should last. A cycle_ticks value of 1
+  can be used to request the fastest possible cycle time. The "value"
+  parameter is between 0 and 255 with 0 indicating a full off state
+  and 255 indicating a full on state. This command may be useful for
+  enabling CPU and nozzle cooling fans.
+
+* send_spi_message pin=%u msg=%*s : This command can be used to
+  transmit messages to a serial-peripheral-interface (SPI) component
+  connected to the micro-controller. It has been used to configure the
+  startup settings of AD5206 digipots. The 'pin' parameter specifies
+  the chip select line to use during the transmission. The 'msg'
+  indicates the binary message to transmit to the given chip.
+
+Firmware configuration
+======================
+
+Most commands in the firmware require an initial setup before they can
+be successfully invoked. This section provides a high-level overview
+of the micro-controller configuration process. This section and the
+following sections are likely only of interest to developers
+interested in the internal details of Klipper.
+
+When the host first connects to the firmware it always starts by
+obtaining the firmware's data dictionary (see [protocol](Protocol.md)
+for more information). After the data dictionary is obtained the host
+will check if the firmware is in a "configured" state and configure it
+if not. Configuration involves the following phases:
+
+* get_config : The host starts by checking if the firmware is already
+  configured. The firmware responds to this command with a "config"
+  response message. At micro-controller power-on the firmware always
+  starts in an unconfigured state. It remains in this state until the
+  host completes the configuration processes (by issuing a
+  finalize_config command). If the firmware is already configured (and
+  is configured with the desired settings) from a previous
+  host/firmware session then no further action is needed by the host
+  and the configuration process ends successfully.
+
+* allocate_oids count=%c : This command is issued to inform the
+  firmware the maximum number of object-ids (oid) that the host
+  requires. It is only valid to issue this command once. An oid is an
+  integer identifier allocated to each stepper, each endstop, and each
+  schedulable gpio pin. The host determines in advance the number of
+  oids it will require to operate the hardware and passes this to the
+  firmware so that the firmware may allocate sufficient memory to
+  store a mapping from oid to internal firmware object.
+
+* config_XXX oid=%c ... : By convention any command starting with the
+  "config_" prefix creates a new firmware object and assigns the given
+  oid to it. For example, the config_digital_out command will
+  configure the specified pin as a digital output GPIO and create an
+  internal object that the host can use to schedule changes to the
+  given GPIO. The oid parameter passed into the config command is
+  selected by the host and must be between zero and the maximum count
+  supplied in the allocate_oids command. The config commands may only
+  be run when the firmware is not in a configured state (ie, prior to
+  the host sending finalize_config) and after the allocate_oids
+  command has been sent.
+
+* finalize_config crc=%u : The finalize_config command transitions the
+  firmware from an unconfigured state to a configured state. The crc
+  parameter passed to the firmware is stored in the firmware and
+  provided back to the host in "config" response messages. By
+  convention, the host takes a 32bit CRC of the firmware configuration
+  it will request and at the start of subsequent host/firmware
+  communication sessions it checks that the CRC stored in the firmware
+  exactly matches its desired CRC. If the CRC does not match then the
+  host knows the firmware has not been configured in the state desired
+  by the host.
+
+Common firmware objects
+-----------------------
+
+This section lists some commonly used config commands.
+
+* config_digital_out oid=%c pin=%u default_value=%c max_duration=%u :
+  This command creates an internal firmware object for the given GPIO
+  'pin'. The pin will be configured in digital output mode and set to
+  an initial value as specified by 'default_value' (0 for low, 1 for
+  high). Creating a digital_out object allows the host to schedule
+  GPIO updates for the given pin at specified times (see the
+  schedule_digital_out command described below). Should the firmware
+  go into shutdown mode then all configured digital_out objects will
+  be set back to their default values. The 'max_duration' parameter is
+  used to implement a safety check - if it is non-zero then it is the
+  maximum number of clock ticks that the host may set the given GPIO
+  to a non-default value without further updates. For example, if the
+  default_value is zero and the max_duration is 16000 then if the host
+  sets the gpio to a value of one then it must schedule another update
+  to the gpio pin (to either zero or one) within 16000 clock
+  ticks. This safety feature can be used with heater pins to ensure
+  the host does not set the heater to a value of one and then go
+  off-line.
+
+* config_pwm_out oid=%c pin=%u cycle_ticks=%u default_value=%c
+  max_duration=%u : This command creates an internal object for
+  hardware based PWM pins that the host may schedule updates for. Its
+  usage is analogous to config_digital_out - see the description of
+  the 'set_pwm_out' and 'config_digital_out' commands for parameter
+  description.
+
+* config_soft_pwm_out oid=%c pin=%u cycle_ticks=%u default_value=%c
+  max_duration=%u : This command creates an internal firmware object
+  for software implemented PWM. Unlike hardware pwm pins, a software
+  pwm object does not require any special hardware support (other than
+  the ability to configure the pin as a digital output GPIO). Because
+  the output switching is implemented in the software of the firmware,
+  it is recommended that the cycle_ticks parameter correspond to a
+  time of 10ms or greater. See the description of the 'set_pwm_out'
+  and 'config_digital_out' commands for parameter description.
+
+* config_analog_in oid=%c pin=%u : This command is used to configure a
+  pin in analog input sampling mode. Once configured, the pin can be
+  sampled at regular interval using the query_analog_in command (see
+  below).
+
+* config_stepper oid=%c step_pin=%c dir_pin=%c min_stop_interval=%u
+  invert_step=%c : This command creates an internal stepper
+  object. The 'step_pin' and 'dir_pin' parameters specify the step and
+  direction pins respectively; this command will configure them in
+  digital output mode. The 'invert_step' parameter specifies whether a
+  step occurs on a rising edge (invert_step=0) or falling edge
+  (invert_step=1). The 'min_stop_interval' implements a safety
+  feature - it is checked when the firmware finishes all moves for a
+  stepper - if it is non-zero it specifies the minimum number of clock
+  ticks since the last step. It is used as a check on the maximum
+  stepper velocity that a stepper may have before stopping.
+
+* config_end_stop oid=%c pin=%c pull_up=%c stepper_oid=%c : This
+  command creates an internal "endstop" object. It is used to specify
+  the endstop pins and to enable "homing" operations (see the
+  end_stop_home command below). The command will configure the
+  specified pin in digital input mode. The 'pull_up' parameter
+  determines whether hardware provided pullup resistors for the pin
+  (if available) will be enabled. The 'stepper_oid' parameter
+  specifies the oid of an associated stepper for the given endstop -
+  it is used during homing operations.
+
+Common commands
+===============
+
+This section lists some commonly used run-time commands. It is likely
+only of interest to developers looking to gain insight into Klippy.
+
+* schedule_digital_out oid=%c clock=%u value=%c : This command will
+  schedule a change to a digital output GPIO pin at the given clock
+  time. To use this command a 'config_digital_out' command with the
+  same 'oid' parameter must have been issued during firmware
+  configuration.
+
+* schedule_pwm_out oid=%c clock=%u value=%c : Schedules a change to a
+  hardware PWM output pin. See the 'schedule_digital_out' and
+  'config_pwm_out' commands for more info.
+
+* schedule_soft_pwm_out oid=%c clock=%u value=%c : Schedules a change
+  to a software PWM output pin. See the 'schedule_digital_out' and
+  'config_soft_pwm_out' commands for more info.
+
+* query_analog_in oid=%c clock=%u sample_ticks=%u sample_count=%c
+  rest_ticks=%u min_value=%hu max_value=%hu : This command sets up a
+  recurring schedule of analog input samples. To use this command a
+  'config_analog_in' command with the same 'oid' parameter must have
+  been issued during firmware configuration. The samples will start as
+  of 'clock' time, it will report on the obtained value every
+  'rest_ticks' clock ticks, it will over-sample 'sample_count' number
+  of times, and it will pause 'sample_ticks' number of clock ticks
+  between over-sample samples. The 'min_value' and 'max_value'
+  parameters implement a safety feature - the firmware will verify the
+  sampled value (after any oversampling) is always between the
+  supplied range. This is intended for use with pins attached to
+  thermistors controlling heaters - it can be used to check that a
+  heater is within a temperature range.
+
+* get_status : This command causes the firmware to generate a "status"
+  response message. The host sends this command once a second to
+  obtain the value of the micro-controller clock and to estimate the
+  drift between host and micro-controller clocks. It enables the host
+  to accurately estimate the micro-controller clock.
+
+Stepper commands
+----------------
+
+* queue_step oid=%c interval=%u count=%hu add=%hi : This command
+  schedules 'count' number of steps for the given stepper, with
+  'interval' number of clock ticks between each step. The first step
+  will be 'interval' number of clock ticks since the last scheduled
+  step for the given stepper. If 'add' is non-zero then the interval
+  will be adjusted by 'add' amount after each step. This command
+  appends the given interval/count/add sequence to a per-stepper
+  queue. There may be hundreds of these sequences queued during normal
+  operation. New sequence are appended to the end of the queue and as
+  each sequence completes its 'count' number of steps it is popped
+  from the front of the queue. This system allows the firmware to
+  queue potentially hundreds of thousands of steps - all with reliable
+  and predictable schedule times.
+
+* set_next_step_dir oid=%c dir=%c : This command specifies the value
+  of the dir_pin that the next queue_step command will use.
+
+* reset_step_clock oid=%c clock=%u : Normally, step timing is relative
+  to the last step for a given stepper. This command resets the clock
+  so that the next step is relative to the supplied 'clock' time. The
+  host usually only sends this command at the start of a print.
+
+* end_stop_home oid=%c clock=%u rest_ticks=%u pin_value=%c : This
+  command is used during stepper "homing" operations. To use this
+  command a 'config_end_stop' command with the same 'oid' parameter
+  must have been issued during firmware configuration. When invoked,
+  the firmware will sample the endstop pin every 'rest_ticks' clock
+  ticks and check if it has a value equal to 'pin_value'. If the value
+  matches then the movement queue for the associated stepper will be
+  cleared and the stepper will come to an immediate halt. The host
+  uses this command to implement homing - the host instructs the
+  endstop to sample for the endstop trigger and then it issues a
+  series of queue_step commands to the stepper to move it towards the
+  endstop. Once the stepper hits the endstop, the trigger will be
+  detected, the movement halted, and the host notified.
+
+### Move queue
+
+Each queue_step command utilizes an entry in the firmware "move
+queue". The firmware allocates this queue when it receives the
+"finalize_config" command, and it reports the number of available
+queue entries in "config" response messages.
+
+It is the responsibility of the host to ensure that there is available
+space in the queue before sending a queue_step command. The host does
+this by calculating when each queue_step command completes and
+scheduling new queue_step commands accordingly.

docs/Installation.md

@@ -0,0 +1,154 @@
+Klipper is currently in an experimental state. These instructions
+assume the software will run on a Raspberry Pi computer in conjunction
+with OctoPrint. Klipper supports Atmel ATmega based micro-controllers
+and Arduino Due (Atmel SAM3x8e ARM micro-controllers) printers.
+
+It is recommended that a Raspberry Pi 2 or Raspberry Pi 3 computer be
+used as the host. The software will run on a first generation
+Raspberry Pi, but the combined load of OctoPrint, Klipper, and a web
+cam (if applicable) can overwhelm its CPU leading to print stalls.
+
+Prepping an OS image
+====================
+
+Start by installing [OctoPi](https://github.com/guysoft/OctoPi) on the
+Raspberry Pi computer. Use OctoPi v0.13.0 or later - see the
+[octopi releases](https://github.com/guysoft/OctoPi/releases) for
+release information. One should verify that OctoPi boots and that the
+OctoPrint web server works. After connecting to the OctoPrint web
+page, follow the prompt to upgrade OctoPrint to v1.3.0 or later.
+
+After installing OctoPi and upgrading OctoPrint, ssh into the target
+machine (ssh pi@octopi -- password is "raspberry") and run the
+following commands:
+
+```
+sudo apt-get update
+sudo apt-get install libncurses-dev
+sudo apt-get install avrdude gcc-avr binutils-avr avr-libc # AVR toolchain
+sudo apt-get install bossa-cli libnewlib-arm-none-eabi # ARM toolchain
+```
+
+The host software (Klippy) requires a one-time setup - run as the
+regular "pi" user:
+
+```
+virtualenv ~/klippy-env
+~/klippy-env/bin/pip install cffi==1.6.0 pyserial==3.2.1 greenlet==0.4.10
+```
+
+Building Klipper
+================
+
+To obtain Klipper, run the following command on the target machine:
+
+```
+git clone https://github.com/KevinOConnor/klipper
+cd klipper/
+```
+
+To compile the micro-controller code, start by configuring it:
+
+```
+make menuconfig
+```
+
+Select the appropriate micro-controller and serial baud rate. Once
+configured, run:
+
+```
+make
+```
+
+Ignore any warnings you may see about "misspelled signal handler" (it
+is due to a bug fixed in gcc v4.8.3).
+
+Installing Klipper on an AVR micro-controller
+---------------------------------------------
+
+The avrdude package can be used to install the micro-controller code
+on an AVR ATmega chip. The exact syntax of the avrdude command is
+different for each micro-controller. The following is an example
+command for atmega2560 chips:
+
+```
+example-only$ avrdude -C/etc/avrdude.conf -v -patmega2560 -cwiring -P/dev/ttyACM0 -b115200 -D -Uflash:w:/home/pi/klipper/out/klipper.elf.hex:i
+```
+
+Installing Klipper on an Arduino Due
+------------------------------------
+
+Klipper currently uses the Arduino Due USB programming port (it will
+not work when connected to the application USB port). The programming
+port is the USB port closest to the power supply. To flash Klipper to
+the Due connect it to the host machine and run:
+
+```
+stty -F /dev/ttyACM0 1200
+bossac -i -p ttyACM0 -R -e -w -v -b ~/klipper/out/klipper.bin
+```
+
+Setting up the printer configuration
+====================================
+
+It is necessary to configure the printer. This is done by modifying a
+configuration file that resides on the host. Start by copying an
+example configuration and editing it.  For example:
+
+```
+cp ~/klipper/config/example.cfg ~/printer.cfg
+nano printer.cfg
+```
+
+Make sure to look at and update each setting that is appropriate for
+the hardware.
+
+Configuring OctoPrint to use Klippy
+===================================
+
+The OctoPrint web server needs to be configured to communicate with
+the Klippy host software. Using a web-browser, login to the OctoPrint
+web page, and navigate to the Settings tab. Then configure the
+following items:
+
+Under "Serial Connection" in "Additional serial ports" add
+"/tmp/printer". Then click "Save".
+
+Enter the Settings tab again and under "Serial Connection" change the
+"Serial Port" setting to "/tmp/printer". Change the Baudrate field to
+250000 (this buad rate field is not related to the firmware baudrate
+and may be safely left at 250000). Unselect the "Not only cancel
+ongoing prints but also disconnect..." checkbox.
+
+Under the "Features" tab, unselect "Enable SD support". Then click
+"Save".
+
+Running the host software
+=========================
+
+The host software is executed by running the following as the regular
+"pi" user:
+
+```
+~/klippy-env/bin/python ~/klipper/klippy/klippy.py ~/printer.cfg -l /tmp/klippy.log < /dev/null > /dev/null 2>&1 &
+```
+
+Once Klippy is running, use a web-browser and navigate to the
+OctoPrint web site. Under the "Connection" tab (on the left of the
+main page) make sure the "Serial Port" is set to "/tmp/printer" and
+click "Connect". (If "/tmp/printer" is not an available selection then
+try reloading the page.)
+
+Once connected, navigate to the "Terminal" tab and type "status"
+(without the quotes) into the command entry box and click "Send". If
+the Klippy config file was successfully read, and the micro-controller
+was successfully found and configured, then this command will report
+that the printer is ready. Klippy reports error messages via this
+terminal tab. The "status" command can be used to re-report error
+messages.
+
+In addition to common g-code commands, Klippy supports a few extended
+commands - "status" is an example of one of these commands. Use the
+"help" command to get a list of other extended commands. In
+particular, note the "restart" command - use this command to reload
+the Klippy config file after any changes.

docs/Overview.md

@@ -0,0 +1,20 @@
+See [installation](Installation.md) for information on compiling,
+installing, and running Klipper. Read [features](Features.md) for a
+high-level description of useful capabilities. The history of releases
+is available at [releases](Releases.md).
+
+There are also several documents available for developers interested
+in understanding how Klipper works:
+
+See [code overview](Code_Overview.md) for information on the structure
+and layout of the Klipper code.
+
+See [protocol](Protocol.md) for information on the messaging protocol
+between host and firmware. See also
+[firmware commands](Firmware_Commands.md) for a high-level description
+of common commands implemented in the firmware.
+
+See [debugging](Debugging.md) for information on how to test and debug
+Klipper.
+
+See [todo](Todo.md) for information on possible future code features.

docs/Protocol.md

@@ -0,0 +1,340 @@
+The Klipper transmission protocol can be thought of, at a high level,
+as a series of command and response strings that are compressed,
+transmitted over a serial line, and then processed at the receiving
+side. An example series of commands in uncompressed human-readable
+format might look like:
+
+```
+set_digital_out pin=86 value=1
+set_digital_out pin=85 value=1
+schedule_digital_out oid=8 clock=4000000 value=0
+queue_step oid=7 interval=7458 count=10 add=331
+queue_step oid=7 interval=11717 count=4 add=1281
+```
+
+See the [firmware commands](Firmware_Commands.md) document for
+information on available commands. See the [debugging](Debugging.md)
+document for information on how to translate a G-Code file into its
+corresponding human-readable firmware commands.
+
+This page provides a high-level description of the Klipper
+transmission protocol itself. It describes how messages are declared,
+encoded in binary format (the "compression" scheme), and transmitted.
+
+The goal of the protocol is to enable an error-free communication
+channel between the host and firmware that is low-latency,
+low-bandwidth, and low-complexity for the firmware.
+
+Firmware Interface
+==================
+
+The Klipper transmission protocol can be thought of as a
+[RPC](https://en.wikipedia.org/wiki/Remote_procedure_call) mechanism
+between firmware and host. The firmware declares the commands that the
+host may invoke along with the response messages that it can
+generate. The host uses that information to command the firmware to
+perform actions and to interpret the results.
+
+Declaring commands
+------------------
+
+The firmware declares a "command" by using the DECL_COMMAND() macro in
+the C code. For example:
+
+```
+DECL_COMMAND(command_set_digital_out, "set_digital_out pin=%u value=%c");
+```
+
+The above declares a command named "set_digital_out". This allows the
+host to "invoke" this command which would cause the
+command_set_digital_out() C function to be executed in the
+firmware. The above also indicates that the command takes two integer
+parameters. When the command_set_digital_out() C code is executed, it
+will be passed an array containing these two integers - the first
+corresponding to the 'pin' and the second corresponding to the
+'value'.
+
+In general, the parameters are described with printf() style syntax
+(eg, "%u"). The formatting directly corresponds to the human-readable
+view of commands (eg, "set_digital_out pin=86 value=1"). In the above
+example, "value=" is a parameter name and "%c" indicates the parameter
+is an integer. Internally, the parameter name is only used as
+documentation. In this example, the "%c" is also used as documentation
+to indicate the expected integer is 1 byte in size (the declared
+integer size does not impact the parsing or encoding).
+
+At firmware compile time, the build will collect all commands declared
+with DECL_COMMAND(), determine their parameters, and arrange for them
+to be callable.
+
+Declaring responses
+-------------------
+
+To send information from the firmware to the host a "response" is
+generated. These are both declared and transmitted using the sendf() C
+macro. For example:
+
+```
+sendf("status clock=%u status=%c", sched_read_time(), sched_is_shutdown());
+```
+
+The above transmits a "status" response message that contains two
+integer parameters ("clock" and "status"). At firmware compile time
+the build automatically finds all sendf() calls and generates encoders
+for them. The first parameter of the sendf() function describes the
+response and it is in the same format as command declarations.
+
+The host can arrange to register a callback function for each
+response. So, in effect, commands allow the host to invoke C functions
+in the firmware and responses allow the firmware to invoke code in the
+host.
+
+The firmware should only invoke sendf() from command or task handlers,
+and it should not be invoked from interrupts or timers. The firmware
+does not need to issue a sendf() in response to a received command, it
+is not limited in the number of times sendf() may be invoked, and it
+may invoke sendf() at any time from a task handler.
+
+### Output responses
+
+To simplify debugging, the firmware also has an output() C
+function. For example:
+
+```
+output("The value of %u is %s with size %u.", x, buf, buf_len);
+```
+
+The output() function is similar in usage to printf() - it is intended
+to generate and format arbitrary messages for human consumption. It is
+a wrapper around sendf() and as with sendf() it should not be called
+from interrupts or timers.
+
+Declaring constants
+-------------------
+
+The firmware can also define constants to be exported.  For example,
+the following:
+
+```
+DECL_CONSTANT(SERIAL_BAUD, 250000);
+```
+
+would export a constant named "SERIAL_BAUD" with a value of 250000
+from the firmware to the host.
+
+Low-level message encoding
+==========================
+
+To accomplish the above RPC mechanism, each command and response is
+encoded into a binary format for transmission. This section describes
+the transmission system.
+
+Message Blocks
+--------------
+
+All data sent from host to firmware and vice-versa are contained in
+"message blocks". A message block has a two byte header and a three
+byte trailer.  The format of a message block is:
+
+```
+<1 byte length><1 byte sequence><n-byte content><2 byte crc><1 byte sync>
+```
+
+The length byte contains the number of bytes in the message block
+including the header and trailer bytes (thus the minimum message
+length is 5 bytes). The maximum message block length is currently 64
+bytes. The sequence byte contains a 4 bit sequence number in the
+low-order bits and the high-order bits always contain 0x10 (the
+high-order bits are reserved for future use). The content bytes
+contain arbitrary data and its format is described in the following
+section. The crc bytes contain a 16bit CCITT
+[CRC](https://en.wikipedia.org/wiki/Cyclic_redundancy_check) of the
+message block including the header bytes but excluding the trailer
+bytes. The sync byte is 0x7e.
+
+The format of the message block is inspired by
+[HDLC](https://en.wikipedia.org/wiki/High-Level_Data_Link_Control)
+message frames. Like in HDLC, the message block may optionally contain
+an additional sync character at the start of the block. Unlike in
+HDLC, a sync character is not exclusive to the framing and may be
+present in the message block content.
+
+Message Block Contents
+----------------------
+
+Each message block sent from host to firmware contains a series of
+zero or more message commands in its contents. Each command starts
+with a Variable Length Quantity (VLQ) encoded integer command-id
+followed by zero or more VLQ parameters for the given command.
+
+As an example, the following four commands might be placed in a single
+message block:
+
+```
+set_digital_out pin=86 value=1
+set_digital_out pin=85 value=0
+get_config
+get_status
+```
+
+and encoded into the following eight VLQ integers:
+
+```
+<id_set_digital_out><86><1><id_set_digital_out><85><0><id_get_config><id_get_status>
+```
+
+In order to encode and parse the message contents, both the host and
+firmware must agree on the command ids and the number of parameters
+each command has. So, in the above example, both the host and firmware
+would know that "id_set_digital_out" is always followed by two
+parameters, and "id_get_config" and "id_get_status" have zero
+parameters. The host and firmware share a "data dictionary" that maps
+the command descriptions (eg, "set_digital_out pin=%u value=%c") to
+their integer command-ids. When processing the data, the parser will
+know to expect a specific number of VLQ encoded parameters following a
+given command id.
+
+The message contents for blocks sent from firmware to host follow the
+same format. The identifiers in these messages are "response ids", but
+they serve the same purpose and follow the same encoding rules. In
+practice, message blocks sent from the firmware to the host never
+contain more than one response in the message block contents.
+
+### Variable Length Quantities
+
+See the [wikipedia article](https://en.wikipedia.org/wiki/Variable-length_quantity)
+for more information on the general format of VLQ encoded
+integers. Klipper uses an encoding scheme that supports both positive
+and negative integers. Integers close to zero use less bytes to encode
+and positive integers typically encode using less bytes than negative
+integers. The following table shows the number of bytes each integer
+takes to encode:
+
+| Integer                   | Encoded size |
+|---------------------------|--------------|
+| -32 .. 95                 | 1            |
+| -4096 .. 12287            | 2            |
+| -524288 .. 1572863        | 3            |
+| -67108864 .. 201326591    | 4            |
+| -2147483648 .. 4294967295 | 5            |
+
+### Variable length strings
+
+As an exception to the above encoding rules, if a parameter to a
+command or response is a dynamic string then the parameter is not
+encoded as a simple VLQ integer. Instead it is encoded by transmitting
+the length as a VLQ encoded integer followed by the contents itself:
+
+```
+<VLQ encoded length><n-byte contents>
+```
+
+The command descriptions found in the data dictionary allow both the
+host and firmware to know which command parameters use simple VLQ
+encoding and which parameters use string encoding.
+
+Data Dictionary
+===============
+
+In order for meaningful communications to be established between
+firmware and host, both sides must agree on a "data dictionary". This
+data dictionary contains the integer identifiers for commands and
+responses along with their descriptions.
+
+At compile time the firmware build uses the contents of DECL_COMMAND()
+and sendf() macros to generate the data dictionary. The build
+automatically assigns unique identifiers to each command and
+response. This system allows both the host and firmware code to
+seamlessly use descriptive human-readable names while still using
+minimal bandwidth.
+
+The host queries the data dictionary when it first connects to the
+firmware. Once the host downloads the data dictionary from the
+firmware, it uses that data dictionary to encode all commands and to
+parse all responses from the firmware. The host must therefore handle
+a dynamic data dictionary. However, to keep the firmware simple, the
+firmware always uses its static (compiled in) data dictionary.
+
+The data dictionary is queried by sending "identify" commands to the
+firmware. The firmware will respond to each identify command with an
+"identify_response" message. Since these two commands are needed prior
+to obtaining the data dictionary, their integer ids and parameter
+types are hard-coded in both the firmware and the host. The
+"identify_response" response id is 0, the "identify" command id
+is 1. Other than having hard-coded ids the identify command and its
+response are declared and transmitted the same way as other commands
+and responses. No other command or response is hard-coded.
+
+The format of the transmitted data dictionary itself is a zlib
+compressed JSON string. The firmware compile process generates the
+string, compresses it, and stores it in the text section of the
+firmware. The data dictionary can be much larger than the maximum
+message block size - the host downloads it by sending multiple
+identify commands requesting progressive chunks of the data
+dictionary. Once all chunks are obtained the host will assemble the
+chunks, uncompress the data, and parse the contents.
+
+In addition to information on the communication protocol, the data
+dictionary also contains firmware version, constants (as defined by
+DECL_CONSTANT), and static strings.
+
+Static Strings
+--------------
+
+To reduce bandwidth the data dictionary also contains a set of static
+strings known to the firmware. This is useful when sending messages
+from firmware to host. For example, if the firmware were to run:
+
+```
+shutdown("Unable to handle command");
+```
+
+The error message would be encoded and sent using a single VLQ. The
+host uses the data dictionary to resolve VLQ encoded static string ids
+to their associated human-readable strings.
+
+Message flow
+============
+
+Message commands sent from host to firmware are intended to be
+error-free. The firmware will check the CRC and sequence numbers in
+each message block to ensure the commands are accurate and
+in-order. The firmware always processes message blocks in-order -
+should it receive a block out-of-order it will discard it and any
+other out-of-order blocks until it receives blocks with the correct
+sequencing.
+
+The low-level host code implements an automatic retransmission system
+for lost and corrupt message blocks sent to the firmware. To
+facilitate this, the firmware transmits an "ack message block" after
+each successfully received message block. The host schedules a timeout
+after sending each block and it will retransmit should the timeout
+expire without receiving a corresponding "ack". In addition, if the
+firmware detects a corrupt or out-of-order block it may transmit a
+"nak message block" to facilitate fast retransmission.
+
+An "ack" is a message block with empty content (ie, a 5 byte message
+block) and a sequence number greater than the last received host
+sequence number. A "nak" is a message block with empty content and a
+sequence number less than the last received host sequence number.
+
+The protocol facilitates a "window" transmission system so that the
+host can have many outstanding message blocks in-flight at a
+time. (This is in addition to the many commands that may be present in
+a given message block.) This allows maximum bandwidth utilization even
+in the event of transmission latency. The timeout, retransmit,
+windowing, and ack mechanism are inspired by similar mechanisms in
+[TCP](https://en.wikipedia.org/wiki/Transmission_Control_Protocol).
+
+In the other direction, message blocks sent from firmware to host are
+designed to be error-free, but they do not have assured
+transmission. (Responses should not be corrupt, but they may go
+missing.) This is done to keep the implementation in the firmware
+simple. There is no automatic retransmission system for responses -
+the high-level code is expected to be capable of handling an
+occasional missing response (usually by re-requesting the content or
+setting up a recurring schedule of response transmission). The
+sequence number field in message blocks sent to the host is always one
+greater than the last received sequence number of message blocks
+received from the host. It is not used to track sequences of response
+message blocks.

docs/Releases.md

@@ -0,0 +1,38 @@
+History of Klipper releases. Please see
+[installation](Installation.md) for information on installing Klipper.
+
+Klipper 0.3.0
+=============
+
+Available on 20161223. Major changes in this release:
+
+* Improved documentation
+* Support for robots with delta kinematics
+* Support for Arduino Due micro-controller (ARM cortex-M3)
+* Support for USB based AVR micro-controllers
+* Support for "pressure advance" algorithm - it reduces ooze during
+  prints.
+* New "stepper phased based endstop" feature - enables higher
+  precision on endstop homing.
+* Support for "extended g-code" commands such as "help", "restart",
+  and "status".
+* Support for reloading the Klipper config and restarting the host
+  software by issuing a "restart" command from the terminal.
+* Stepper performance improvements (20Mhz AVRs up to 158K steps per
+  second).
+* Improved error reporting. Most errors now shown via the terminal
+  along with help on how to resolve.
+* Several bug fixes and code cleanups
+
+Klipper 0.2.0
+=============
+
+Initial release of Klipper. Available on 20160525. Major features
+available in the initial release include:
+
+* Basic support for cartesian printers (steppers, extruder, heated
+  bed, cooling fan).
+* Support for common g-code commands. Support for interfacing with
+  OctoPrint.
+* Acceleration and lookahead handling
+* Support for AVR micro-controllers via standard serial ports

docs/Todo.md

@@ -0,0 +1,129 @@
+Klipper is currently in an experimental state. There are several
+features still to be implemented.  In no particular order:
+
+Host user interaction
+=====================
+
+* See if there is a better way to report errors. Octoprint sometimes
+  doesn't highlight an error (one has to look in the terminal tab to
+  find the error) and errors written to the log can be non-obvious to
+  a user.
+
+* Improve startup:
+
+ * Provide startup scripts so that Klippy can startup at system
+   bootup.
+
+ * Allow loading of a new config without having to restart the mcu.
+
+* Improve gcode interface:
+
+ * Provide a better way to handle print nozzle z offsets. The M206
+   command is cryptic to use and it is too easy to set the value
+   incorrectly or to forget to set it.
+
+ * Provide a way to temporarily disable endstop checks so that a user
+   can issue commands that potentially move the head past
+   position_min/position_max.
+
+* Improve logging:
+
+ * Automatically roll Klippy log files. The default log file should
+   have the current date in the log file name.
+
+ * Report the Klippy git version in log file. Log the contents of the
+   config file at startup.
+
+ * Possibly collate and report the statistics messages in the log in a
+   more friendly way.
+
+* Possibly support a mechanism for the host to limit maximum velocity
+  so that the mcu is never requested to step at a higher rate than it
+  can support.
+
+Safety features
+===============
+
+* Support loading a valid step range into the firmware after
+  homing. This would provide a sanity check in the firmware that would
+  reduce the risk of the host commanding a stepper motor past its
+  valid step range. To maintain high efficiency in the firmware, the
+  firmware would only need to check periodically (eg, every 100ms)
+  that the stepper is in range.
+
+ * Possibly support periodically querying the endstop switches and use
+   multiple step ranges depending on the switch state. This would
+   enable runtime endstop detection. (However, it's unclear if runtime
+   endstop detection is a good idea because of spurious signals caused
+   by electrical noise.)
+
+* Support validating that heaters are heating at expected rates. This
+  can be useful to detect a sensor failure (eg, thermistor short) that
+  could otherwise cause the PID to command excessive heating.
+
+* Possibly implement host based checking on the ratio between extrude
+  amount and head movement.
+ * Enforce acceleration and speed limits on extruder stepper motor.
+
+Testing features
+================
+
+* Complete the host based simulator. It's possible to compile the
+  firmware for a "host simulator", but that simulator doesn't do
+  anything currently. It would be useful to expand the code to support
+  more error checks, kinematic simulations, and improved logging.
+
+Documentation
+=============
+
+* Document and test running the host software on a Beagle Bone Black.
+
+* Add documentation describing how to perform bed-leveling accurately
+  in Klipper. Improve description of stepper phase based bed leveling.
+
+* Document the kinematic formulas in Klippy. Document how acceleration
+  and jerk limits are enforced.
+
+* Document how one can tune the pressure advance setting.
+
+Hardware features
+=================
+
+* Port firmware to more architectures:
+ * Beagle Bone Black PRU
+ * Smoothieboard / NXP LPC1769 (ARM cortex-M3)
+ * Unix based scheduling; Unix based real-time scheduling
+
+* Support for additional kinematics: scara, corexy, etc.
+
+* Support shared motor enable GPIO lines.
+
+* Support for multiple extruders.
+
+* Support for bed-level probes.
+
+* Possible support for touch panels attached to the micro-controller.
+  (In general, it would be preferable to attach touch panels to the
+  host system and have octoprint interact with the panel directly, but
+  it would also be useful to handle panels already hardwired to the
+  micro-controller.)
+
+* The raspberry pi has the ability to cut power to its USB ports. This
+  feature is useful for resetting micro-controllers that are powered
+  over USB. It would be useful to have a high-level command interface
+  in Klippy to request a micro-controller reset via this mechanism.
+
+* Possibly support printers using multiple micro-controllers.
+
+Misc features
+=============
+
+* Possibly use cubic functions instead of quadratic functions in step
+  compression code.
+
+* Possibly support a "feed forward PID" that takes into account the
+  amount of plastic being extruded. If the extrude rate changes
+  significantly during a print it can cause heating bumps that the PID
+  overcompensates for. The temperature change due to the extrusion
+  rate could be modeled to eliminate these bumps and make the
+  extrusion temperature more consistent.

klippy/cartesian.py

@@ -0,0 +1,147 @@
+# Code for handling the kinematics of cartesian robots
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import logging
+import stepper, homing
+
+StepList = (0, 1, 2)
+
+class CartKinematics:
+    def __init__(self, printer, config):
+        self.steppers = [stepper.PrinterStepper(
+            printer, config.getsection('stepper_' + n), n)
+                         for n in ['x', 'y', 'z']]
+        self.max_z_velocity = config.getfloat('max_z_velocity', 9999999.9)
+        self.max_z_accel = config.getfloat('max_z_accel', 9999999.9)
+        self.need_motor_enable = True
+        self.limits = [(1.0, -1.0)] * 3
+    def set_max_jerk(self, max_xy_halt_velocity, max_accel):
+        self.steppers[0].set_max_jerk(max_xy_halt_velocity, max_accel)
+        self.steppers[1].set_max_jerk(max_xy_halt_velocity, max_accel)
+        self.steppers[2].set_max_jerk(0., self.max_z_accel)
+    def build_config(self):
+        for stepper in self.steppers:
+            stepper.build_config()
+    def set_position(self, newpos):
+        for i in StepList:
+            s = self.steppers[i]
+            s.mcu_stepper.set_position(int(newpos[i]*s.inv_step_dist + 0.5))
+    def home(self, homing_state):
+        # Each axis is homed independently and in order
+        for axis in homing_state.get_axes():
+            s = self.steppers[axis]
+            self.limits[axis] = (s.position_min, s.position_max)
+            # Determine moves
+            if s.homing_positive_dir:
+                pos = s.position_endstop - 1.5*(
+                    s.position_endstop - s.position_min)
+                rpos = s.position_endstop - s.homing_retract_dist
+                r2pos = rpos - s.homing_retract_dist
+            else:
+                pos = s.position_endstop + 1.5*(
+                    s.position_max - s.position_endstop)
+                rpos = s.position_endstop + s.homing_retract_dist
+                r2pos = rpos + s.homing_retract_dist
+            # Initial homing
+            homepos = [None, None, None, None]
+            homepos[axis] = s.position_endstop
+            coord = [None, None, None, None]
+            coord[axis] = pos
+            homing_state.home(list(coord), homepos, [s], s.homing_speed)
+            # Retract
+            coord[axis] = rpos
+            homing_state.retract(list(coord), s.homing_speed)
+            # Home again
+            coord[axis] = r2pos
+            homing_state.home(
+                list(coord), homepos, [s], s.homing_speed/2.0, second_home=True)
+            # Set final homed position
+            coord[axis] = s.position_endstop + s.get_homed_offset()*s.step_dist
+            homing_state.set_homed_position(coord)
+    def motor_off(self, move_time):
+        self.limits = [(1.0, -1.0)] * 3
+        for stepper in self.steppers:
+            stepper.motor_enable(move_time, 0)
+        self.need_motor_enable = True
+    def _check_motor_enable(self, move_time, move):
+        need_motor_enable = False
+        for i in StepList:
+            if move.axes_d[i]:
+                self.steppers[i].motor_enable(move_time, 1)
+            need_motor_enable |= self.steppers[i].need_motor_enable
+        self.need_motor_enable = need_motor_enable
+    def query_endstops(self, print_time):
+        endstops = [(s, s.query_endstop(print_time)) for s in self.steppers]
+        return [(s.name, es.query_endstop_wait()) for s, es in endstops]
+    def _check_endstops(self, move):
+        end_pos = move.end_pos
+        for i in StepList:
+            if (move.axes_d[i]
+                and (end_pos[i] < self.limits[i][0]
+                     or end_pos[i] > self.limits[i][1])):
+                if self.limits[i][0] > self.limits[i][1]:
+                    raise homing.EndstopMoveError(
+                        end_pos, "Must home axis first")
+                raise homing.EndstopMoveError(end_pos)
+    def check_move(self, move):
+        limits = self.limits
+        xpos, ypos = move.end_pos[:2]
+        if (xpos < limits[0][0] or xpos > limits[0][1]
+            or ypos < limits[1][0] or ypos > limits[1][1]):
+            self._check_endstops(move)
+        if not move.axes_d[2]:
+            # Normal XY move - use defaults
+            return
+        # Move with Z - update velocity and accel for slower Z axis
+        self._check_endstops(move)
+        z_ratio = move.move_d / abs(move.axes_d[2])
+        move.limit_speed(
+            self.max_z_velocity * z_ratio, self.max_z_accel * z_ratio)
+    def move(self, move_time, move):
+        if self.need_motor_enable:
+            self._check_motor_enable(move_time, move)
+        inv_accel = 1. / move.accel
+        inv_cruise_v = 1. / move.cruise_v
+        for i in StepList:
+            if not move.axes_d[i]:
+                continue
+            mcu_stepper = self.steppers[i].mcu_stepper
+            mcu_time = mcu_stepper.print_to_mcu_time(move_time)
+            step_pos = mcu_stepper.commanded_position
+            inv_step_dist = self.steppers[i].inv_step_dist
+            step_offset = step_pos - move.start_pos[i] * inv_step_dist
+            steps = move.axes_d[i] * inv_step_dist
+            move_step_d = move.move_d / abs(steps)
+
+            # Acceleration steps
+            accel_multiplier = 2.0 * move_step_d * inv_accel
+            if move.accel_r:
+                #t = sqrt(2*pos/accel + (start_v/accel)**2) - start_v/accel
+                accel_time_offset = move.start_v * inv_accel
+                accel_sqrt_offset = accel_time_offset**2
+                accel_steps = move.accel_r * steps
+                count = mcu_stepper.step_sqrt(
+                    mcu_time - accel_time_offset, accel_steps, step_offset
+                    , accel_sqrt_offset, accel_multiplier)
+                step_offset += count - accel_steps
+                mcu_time += move.accel_t
+            # Cruising steps
+            if move.cruise_r:
+                #t = pos/cruise_v
+                cruise_multiplier = move_step_d * inv_cruise_v
+                cruise_steps = move.cruise_r * steps
+                count = mcu_stepper.step_factor(
+                    mcu_time, cruise_steps, step_offset, cruise_multiplier)
+                step_offset += count - cruise_steps
+                mcu_time += move.cruise_t
+            # Deceleration steps
+            if move.decel_r:
+                #t = cruise_v/accel - sqrt((cruise_v/accel)**2 - 2*pos/accel)
+                decel_time_offset = move.cruise_v * inv_accel
+                decel_sqrt_offset = decel_time_offset**2
+                decel_steps = move.decel_r * steps
+                count = mcu_stepper.step_sqrt(
+                    mcu_time + decel_time_offset, decel_steps, step_offset
+                    , decel_sqrt_offset, -accel_multiplier)

klippy/chelper.py

@@ -0,0 +1,121 @@
+# Wrapper around C helper code
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import os, logging
+import cffi
+
+COMPILE_CMD = "gcc -Wall -g -O -shared -fPIC -o %s %s"
+SOURCE_FILES = ['stepcompress.c', 'serialqueue.c', 'pyhelper.c']
+DEST_LIB = "c_helper.so"
+OTHER_FILES = ['list.h', 'serialqueue.h', 'pyhelper.h']
+
+defs_stepcompress = """
+    struct stepcompress *stepcompress_alloc(uint32_t max_error
+        , uint32_t queue_step_msgid, uint32_t set_next_step_dir_msgid
+        , uint32_t invert_sdir, uint32_t oid);
+    void stepcompress_free(struct stepcompress *sc);
+    void stepcompress_push(struct stepcompress *sc, double step_clock
+        , int32_t sdir);
+    int32_t stepcompress_push_factor(struct stepcompress *sc
+        , double steps, double step_offset
+        , double clock_offset, double factor);
+    int32_t stepcompress_push_sqrt(struct stepcompress *sc
+        , double steps, double step_offset
+        , double clock_offset, double sqrt_offset, double factor);
+    int32_t stepcompress_push_delta_const(struct stepcompress *sc
+        , double clock_offset, double dist, double start_pos
+        , double inv_velocity, double step_dist, double height
+        , double closestxy_d, double closest_height2, double movez_r);
+    int32_t stepcompress_push_delta_accel(struct stepcompress *sc
+        , double clock_offset, double dist, double start_pos
+        , double accel_multiplier, double step_dist, double height
+        , double closestxy_d, double closest_height2, double movez_r);
+    void stepcompress_reset(struct stepcompress *sc, uint64_t last_step_clock);
+    void stepcompress_queue_msg(struct stepcompress *sc
+        , uint32_t *data, int len);
+    uint32_t stepcompress_get_errors(struct stepcompress *sc);
+
+    struct steppersync *steppersync_alloc(struct serialqueue *sq
+        , struct stepcompress **sc_list, int sc_num, int move_num);
+    void steppersync_free(struct steppersync *ss);
+    void steppersync_flush(struct steppersync *ss, uint64_t move_clock);
+"""
+
+defs_serialqueue = """
+    #define MESSAGE_MAX 64
+    struct pull_queue_message {
+        uint8_t msg[MESSAGE_MAX];
+        int len;
+        double sent_time, receive_time;
+    };
+
+    struct serialqueue *serialqueue_alloc(int serial_fd, int write_only);
+    void serialqueue_exit(struct serialqueue *sq);
+    void serialqueue_free(struct serialqueue *sq);
+    struct command_queue *serialqueue_alloc_commandqueue(void);
+    void serialqueue_free_commandqueue(struct command_queue *cq);
+    void serialqueue_send(struct serialqueue *sq, struct command_queue *cq
+        , uint8_t *msg, int len, uint64_t min_clock, uint64_t req_clock);
+    void serialqueue_encode_and_send(struct serialqueue *sq
+        , struct command_queue *cq, uint32_t *data, int len
+        , uint64_t min_clock, uint64_t req_clock);
+    void serialqueue_pull(struct serialqueue *sq, struct pull_queue_message *pqm);
+    void serialqueue_set_baud_adjust(struct serialqueue *sq, double baud_adjust);
+    void serialqueue_set_clock_est(struct serialqueue *sq, double est_clock
+        , double last_ack_time, uint64_t last_ack_clock);
+    void serialqueue_flush_ready(struct serialqueue *sq);
+    void serialqueue_get_stats(struct serialqueue *sq, char *buf, int len);
+    int serialqueue_extract_old(struct serialqueue *sq, int sentq
+        , struct pull_queue_message *q, int max);
+"""
+
+defs_pyhelper = """
+    void set_python_logging_callback(void (*func)(const char *));
+"""
+
+# Return the list of file modification times
+def get_mtimes(srcdir, filelist):
+    out = []
+    for filename in filelist:
+        pathname = os.path.join(srcdir, filename)
+        try:
+            t = os.path.getmtime(pathname)
+        except os.error:
+            continue
+        out.append(t)
+    return out
+
+# Check if the code needs to be compiled
+def check_build_code(srcdir):
+    src_times = get_mtimes(srcdir, SOURCE_FILES + OTHER_FILES)
+    obj_times = get_mtimes(srcdir, [DEST_LIB])
+    if not obj_times or max(src_times) > min(obj_times):
+        logging.info("Building C code module")
+        srcfiles = [os.path.join(srcdir, fname) for fname in SOURCE_FILES]
+        destlib = os.path.join(srcdir, DEST_LIB)
+        os.system(COMPILE_CMD % (destlib, ' '.join(srcfiles)))
+
+FFI_main = None
+FFI_lib = None
+pyhelper_logging_callback = None
+
+# Return the Foreign Function Interface api to the caller
+def get_ffi():
+    global FFI_main, FFI_lib, pyhelper_logging_callback
+    if FFI_lib is None:
+        srcdir = os.path.dirname(os.path.realpath(__file__))
+        check_build_code(srcdir)
+        FFI_main = cffi.FFI()
+        FFI_main.cdef(defs_stepcompress)
+        FFI_main.cdef(defs_serialqueue)
+        FFI_main.cdef(defs_pyhelper)
+        FFI_lib = FFI_main.dlopen(os.path.join(srcdir, DEST_LIB))
+        # Setup error logging
+        def logging_callback(msg):
+            logging.error(FFI_main.string(msg))
+        pyhelper_logging_callback = FFI_main.callback(
+            "void(const char *)", logging_callback)
+        FFI_lib.set_python_logging_callback(pyhelper_logging_callback)
+    return FFI_main, FFI_lib

klippy/console.py

@@ -0,0 +1,116 @@
+#!/usr/bin/env python
+# Script to implement a test console with firmware over serial port
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import sys, optparse, os, re, logging
+
+import reactor, serialhdl, pins, util, msgproto
+
+re_eval = re.compile(r'\{(?P<eval>[^}]*)\}')
+
+class KeyboardReader:
+    def __init__(self, ser, reactor):
+        self.ser = ser
+        self.reactor = reactor
+        self.fd = sys.stdin.fileno()
+        util.set_nonblock(self.fd)
+        self.pins = None
+        self.data = ""
+        reactor.register_fd(self.fd, self.process_kbd)
+        self.connect_timer = reactor.register_timer(self.connect, reactor.NOW)
+        self.local_commands = { "PINS": self.set_pin_map, "SET": self.set_var }
+        self.eval_globals = {}
+    def connect(self, eventtime):
+        self.ser.connect()
+        self.reactor.unregister_timer(self.connect_timer)
+        return self.reactor.NEVER
+    def update_evals(self, eventtime):
+        f = int(self.ser.msgparser.config.get('CLOCK_FREQ', 1))
+        c = self.ser.get_clock(eventtime)
+        self.eval_globals['freq'] = f
+        self.eval_globals['clock'] = int(c)
+    def set_pin_map(self, parts):
+        mcu = self.ser.msgparser.config['MCU']
+        self.pins = pins.map_pins(parts[1], mcu)
+    def set_var(self, parts):
+        val = parts[2]
+        try:
+            val = int(val)
+        except ValueError:
+            try:
+                val = float(val)
+            except ValueError:
+                pass
+        self.eval_globals[parts[1]] = val
+    def lookup_pin(self, value):
+        if self.pins is None:
+            self.pins = pins.mcu_to_pins(self.ser.msgparser.config['MCU'])
+        return self.pins[value]
+    def translate(self, line, eventtime):
+        evalparts = re_eval.split(line)
+        if len(evalparts) > 1:
+            self.update_evals(eventtime)
+            try:
+                for i in range(1, len(evalparts), 2):
+                    evalparts[i] = str(eval(evalparts[i], self.eval_globals))
+            except:
+                print "Unable to evaluate: ", line
+                return None
+            line = ''.join(evalparts)
+            print "Eval:", line
+        if self.pins is None and self.ser.msgparser.config:
+            self.pins = pins.mcu_to_pins(self.ser.msgparser.config['MCU'])
+        if self.pins is not None:
+            try:
+                line = pins.update_command(line, self.pins).strip()
+            except:
+                print "Unable to map pin: ", line
+                return None
+        if line:
+            parts = line.split()
+            if parts[0] in self.local_commands:
+                self.local_commands[parts[0]](parts)
+                return None
+        try:
+            msg = self.ser.msgparser.create_command(line)
+        except msgproto.error, e:
+            print "Error:", e
+            return None
+        return msg
+    def process_kbd(self, eventtime):
+        self.data += os.read(self.fd, 4096)
+
+        kbdlines = self.data.split('\n')
+        for line in kbdlines[:-1]:
+            line = line.strip()
+            cpos = line.find('#')
+            if cpos >= 0:
+                line = line[:cpos]
+                if not line:
+                    continue
+            msg = self.translate(line.strip(), eventtime)
+            if msg is None:
+                continue
+            self.ser.send(msg)
+        self.data = kbdlines[-1]
+
+def main():
+    usage = "%prog [options] <serialdevice> <baud>"
+    opts = optparse.OptionParser(usage)
+    options, args = opts.parse_args()
+    serialport, baud = args
+    baud = int(baud)
+
+    logging.basicConfig(level=logging.DEBUG)
+    r = reactor.Reactor()
+    ser = serialhdl.SerialReader(r, serialport, baud)
+    kbd = KeyboardReader(ser, r)
+    try:
+        r.run()
+    except KeyboardInterrupt:
+        sys.stdout.write("\n")
+
+if __name__ == '__main__':
+    main()

klippy/delta.py

@@ -0,0 +1,260 @@
+# Code for handling the kinematics of linear delta robots
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import math, logging
+import stepper, homing
+
+StepList = (0, 1, 2)
+
+class DeltaKinematics:
+    def __init__(self, printer, config):
+        self.steppers = [stepper.PrinterStepper(
+            printer, config.getsection('stepper_' + n), n)
+                         for n in ['a', 'b', 'c']]
+        self.need_motor_enable = True
+        self.max_z_velocity = config.getfloat('max_z_velocity', 9999999.9)
+        radius = config.getfloat('delta_radius')
+        arm_length = config.getfloat('delta_arm_length')
+        self.arm_length2 = arm_length**2
+        self.max_xy2 = min(radius, arm_length - radius)**2
+        self.limit_xy2 = -1.
+        tower_height_at_zeros = math.sqrt(self.arm_length2 - radius**2)
+        self.max_z = self.steppers[0].position_max
+        self.limit_z = self.max_z - (arm_length - tower_height_at_zeros)
+        sin = lambda angle: math.sin(math.radians(angle))
+        cos = lambda angle: math.cos(math.radians(angle))
+        self.towers = [
+            (cos(210.)*radius, sin(210.)*radius),
+            (cos(330.)*radius, sin(330.)*radius),
+            (cos(90.)*radius, sin(90.)*radius)]
+    def set_max_jerk(self, max_xy_halt_velocity, max_accel):
+        # XXX - this sets conservative values
+        for stepper in self.steppers:
+            stepper.set_max_jerk(max_xy_halt_velocity, max_accel)
+    def build_config(self):
+        for stepper in self.steppers:
+            stepper.build_config()
+        self.set_position([0., 0., 0.])
+    def _cartesian_to_actuator(self, coord):
+        return [int((math.sqrt(self.arm_length2
+                               - (self.towers[i][0] - coord[0])**2
+                               - (self.towers[i][1] - coord[1])**2) + coord[2])
+                    * self.steppers[i].inv_step_dist + 0.5)
+                for i in StepList]
+    def _actuator_to_cartesian(self, pos):
+        # Based on code from Smoothieware
+        tower1 = list(self.towers[0]) + [pos[0]]
+        tower2 = list(self.towers[1]) + [pos[1]]
+        tower3 = list(self.towers[2]) + [pos[2]]
+
+        s12 = matrix_sub(tower1, tower2)
+        s23 = matrix_sub(tower2, tower3)
+        s13 = matrix_sub(tower1, tower3)
+
+        normal = matrix_cross(s12, s23)
+
+        magsq_s12 = matrix_magsq(s12)
+        magsq_s23 = matrix_magsq(s23)
+        magsq_s13 = matrix_magsq(s13)
+
+        inv_nmag_sq = 1.0 / matrix_magsq(normal)
+        q = 0.5 * inv_nmag_sq
+
+        a = q * magsq_s23 * matrix_dot(s12, s13)
+        b = -q * magsq_s13 * matrix_dot(s12, s23) # negate because we use s12 instead of s21
+        c = q * magsq_s12 * matrix_dot(s13, s23)
+
+        circumcenter = [tower1[0] * a + tower2[0] * b + tower3[0] * c,
+                        tower1[1] * a + tower2[1] * b + tower3[1] * c,
+                        tower1[2] * a + tower2[2] * b + tower3[2] * c]
+
+        r_sq = 0.5 * q * magsq_s12 * magsq_s23 * magsq_s13
+        dist = math.sqrt(inv_nmag_sq * (self.arm_length2 - r_sq))
+
+        return matrix_sub(circumcenter, matrix_mul(normal, dist))
+    def set_position(self, newpos):
+        pos = self._cartesian_to_actuator(newpos)
+        for i in StepList:
+            self.steppers[i].mcu_stepper.set_position(pos[i])
+    def home(self, homing_state):
+        # All axes are homed simultaneously
+        homing_state.set_axes([0, 1, 2])
+        s = self.steppers[0] # Assume homing parameters same for all steppers
+        self.limit_xy2 = self.max_xy2
+        # Initial homing
+        homepos = [0., 0., s.position_endstop, None]
+        coord = list(homepos)
+        coord[2] = -1.5 * math.sqrt(self.arm_length2-self.max_xy2)
+        homing_state.home(list(coord), homepos, self.steppers, s.homing_speed)
+        # Retract
+        coord[2] = homepos[2] - s.homing_retract_dist
+        homing_state.retract(list(coord), s.homing_speed)
+        # Home again
+        coord[2] -= s.homing_retract_dist
+        homing_state.home(list(coord), homepos, self.steppers
+                          , s.homing_speed/2.0, second_home=True)
+        # Set final homed position
+        coord = [(s.mcu_stepper.commanded_position + s.get_homed_offset())
+                 * s.step_dist
+                 for s in self.steppers]
+        homing_state.set_homed_position(self._actuator_to_cartesian(coord))
+    def motor_off(self, move_time):
+        self.limit_xy2 = -1.
+        for stepper in self.steppers:
+            stepper.motor_enable(move_time, 0)
+        self.need_motor_enable = True
+    def _check_motor_enable(self, move_time):
+        for i in StepList:
+            self.steppers[i].motor_enable(move_time, 1)
+        self.need_motor_enable = False
+    def query_endstops(self, print_time):
+        endstops = [(s, s.query_endstop(print_time)) for s in self.steppers]
+        return [(s.name, es.query_endstop_wait()) for s, es in endstops]
+    def check_move(self, move):
+        end_pos = move.end_pos
+        xy2 = end_pos[0]**2 + end_pos[1]**2
+        if xy2 > self.limit_xy2 or end_pos[2] < 0.:
+            if self.limit_xy2 < 0.:
+                raise homing.EndstopMoveError(end_pos, "Must home first")
+            raise homing.EndstopMoveError(end_pos)
+        if end_pos[2] > self.limit_z:
+            if end_pos[2] > self.max_z or xy2 > (self.max_z - end_pos[2])**2:
+                raise homing.EndstopMoveError(end_pos)
+        if move.axes_d[2]:
+            move.limit_speed(self.max_z_velocity, 9999999.9)
+    def move(self, move_time, move):
+        axes_d = move.axes_d
+        move_d = movexy_d = move.move_d
+        movexy_r = 1.
+        movez_r = 0.
+        inv_movexy_d = 1. / movexy_d
+        if not axes_d[0] and not axes_d[1]:
+            if not axes_d[2]:
+                return
+            movez_r = axes_d[2] * inv_movexy_d
+            movexy_d = movexy_r = inv_movexy_d = 0.
+        elif axes_d[2]:
+            movexy_d = math.sqrt(axes_d[0]**2 + axes_d[1]**2)
+            movexy_r = movexy_d * inv_movexy_d
+            movez_r = axes_d[2] * inv_movexy_d
+            inv_movexy_d = 1. / movexy_d
+
+        if self.need_motor_enable:
+            self._check_motor_enable(move_time)
+
+        origx, origy, origz = move.start_pos[:3]
+
+        accel_t = move.accel_t
+        cruise_end_t = accel_t + move.cruise_t
+        accel_d = move.accel_r * move_d
+        cruise_end_d = accel_d + move.cruise_r * move_d
+
+        inv_cruise_v = 1. / move.cruise_v
+        inv_accel = 1. / move.accel
+        accel_time_offset = move.start_v * inv_accel
+        accel_multiplier = 2.0 * inv_accel
+        accel_offset = move.start_v**2 * 0.5 * inv_accel
+        decel_time_offset = move.cruise_v * inv_accel + cruise_end_t
+        decel_offset = move.cruise_v**2 * 0.5 * inv_accel + cruise_end_d
+
+        for i in StepList:
+            # Find point on line of movement closest to tower
+            towerx_d = self.towers[i][0] - origx
+            towery_d = self.towers[i][1] - origy
+            closestxy_d = (towerx_d*axes_d[0] + towery_d*axes_d[1])*inv_movexy_d
+            tangentxy_d2 = towerx_d**2 + towery_d**2 - closestxy_d**2
+            closest_height2 = self.arm_length2 - tangentxy_d2
+
+            # Calculate accel/cruise/decel portions of move
+            reversexy_d = closestxy_d + math.sqrt(closest_height2)*movez_r
+            accel_up_d = cruise_up_d = decel_up_d = 0.
+            accel_down_d = cruise_down_d = decel_down_d = 0.
+            if reversexy_d <= 0.:
+                accel_down_d = accel_d
+                cruise_down_d = cruise_end_d
+                decel_down_d = move_d
+            elif reversexy_d >= movexy_d:
+                accel_up_d = accel_d
+                cruise_up_d = cruise_end_d
+                decel_up_d = move_d
+            elif reversexy_d < accel_d * movexy_r:
+                accel_up_d = reversexy_d * move_d * inv_movexy_d
+                accel_down_d = accel_d
+                cruise_down_d = cruise_end_d
+                decel_down_d = move_d
+            elif reversexy_d < cruise_end_d * movexy_r:
+                accel_up_d = accel_d
+                cruise_up_d = reversexy_d * move_d * inv_movexy_d
+                cruise_down_d = cruise_end_d
+                decel_down_d = move_d
+            else:
+                accel_up_d = accel_d
+                cruise_up_d = cruise_end_d
+                decel_up_d = reversexy_d * move_d * inv_movexy_d
+                decel_down_d = move_d
+
+            # Generate steps
+            mcu_stepper = self.steppers[i].mcu_stepper
+            mcu_time = mcu_stepper.print_to_mcu_time(move_time)
+            step_pos = mcu_stepper.commanded_position
+            step_dist = self.steppers[i].step_dist
+            height = step_pos*step_dist - origz
+            if accel_up_d > 0.:
+                count = mcu_stepper.step_delta_accel(
+                    mcu_time - accel_time_offset, accel_up_d,
+                    accel_offset, accel_multiplier, step_dist,
+                    height, closestxy_d, closest_height2, movez_r)
+                height += count * step_dist
+            if cruise_up_d > 0.:
+                count = mcu_stepper.step_delta_const(
+                    mcu_time + accel_t, cruise_up_d,
+                    -accel_d, inv_cruise_v, step_dist,
+                    height, closestxy_d, closest_height2, movez_r)
+                height += count * step_dist
+            if decel_up_d > 0.:
+                count = mcu_stepper.step_delta_accel(
+                    mcu_time + decel_time_offset, decel_up_d,
+                    -decel_offset, -accel_multiplier, step_dist,
+                    height, closestxy_d, closest_height2, movez_r)
+                height += count * step_dist
+            if accel_down_d > 0.:
+                count = mcu_stepper.step_delta_accel(
+                    mcu_time - accel_time_offset, accel_down_d,
+                    accel_offset, accel_multiplier, -step_dist,
+                    height, closestxy_d, closest_height2, movez_r)
+                height += count * step_dist
+            if cruise_down_d > 0.:
+                count = mcu_stepper.step_delta_const(
+                    mcu_time + accel_t, cruise_down_d,
+                    -accel_d, inv_cruise_v, -step_dist,
+                    height, closestxy_d, closest_height2, movez_r)
+                height += count * step_dist
+            if decel_down_d > 0.:
+                count = mcu_stepper.step_delta_accel(
+                    mcu_time + decel_time_offset, decel_down_d,
+                    -decel_offset, -accel_multiplier, -step_dist,
+                    height, closestxy_d, closest_height2, movez_r)
+
+
+######################################################################
+# Matrix helper functions for 3x1 matrices
+######################################################################
+
+def matrix_cross(m1, m2):
+    return [m1[1] * m2[2] - m1[2] * m2[1],
+            m1[2] * m2[0] - m1[0] * m2[2],
+            m1[0] * m2[1] - m1[1] * m2[0]]
+
+def matrix_dot(m1, m2):
+    return m1[0] * m2[0] + m1[1] * m2[1] + m1[2] * m2[2]
+
+def matrix_magsq(m1):
+    return m1[0]**2 + m1[1]**2 + m1[2]**2
+
+def matrix_sub(m1, m2):
+    return [m1[0] - m2[0], m1[1] - m2[1], m1[2] - m2[2]]
+
+def matrix_mul(m1, s):
+    return [m1[0]*s, m1[1]*s, m1[2]*s]

klippy/extruder.py

@@ -0,0 +1,148 @@
+# Code for handling printer nozzle extruders
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import logging
+import stepper, heater, homing
+
+class PrinterExtruder:
+    def __init__(self, printer, config):
+        self.heater = heater.PrinterHeater(printer, config)
+        self.stepper = stepper.PrinterStepper(printer, config, 'extruder')
+        self.pressure_advance = config.getfloat('pressure_advance', 0.)
+        self.max_e_velocity = config.getfloat('max_velocity')
+        self.max_e_accel = config.getfloat('max_accel')
+        self.need_motor_enable = True
+        self.extrude_pos = 0.
+    def build_config(self):
+        self.heater.build_config()
+        self.stepper.set_max_jerk(9999999.9, 9999999.9)
+        self.stepper.build_config()
+    def motor_off(self, move_time):
+        self.stepper.motor_enable(move_time, 0)
+        self.need_motor_enable = True
+    def check_move(self, move):
+        if not self.heater.can_extrude:
+            raise homing.EndstopMoveError(
+                move.end_pos, "Extrude below minimum temp")
+        if (not move.do_calc_junction
+            and not move.axes_d[0] and not move.axes_d[1]
+            and not move.axes_d[2]):
+            # Extrude only move - limit accel and velocity
+            move.limit_speed(self.max_e_velocity, self.max_e_accel)
+    def move(self, move_time, move):
+        if self.need_motor_enable:
+            self.stepper.motor_enable(move_time, 1)
+            self.need_motor_enable = False
+        axis_d = move.axes_d[3]
+        extrude_r = abs(axis_d) / move.move_d
+        inv_accel = 1. / (move.accel * extrude_r)
+
+        start_v = move.start_v * extrude_r
+        cruise_v = move.cruise_v * extrude_r
+        end_v = move.end_v * extrude_r
+        accel_t, cruise_t, decel_t = move.accel_t, move.cruise_t, move.decel_t
+        accel_d = move.accel_r * axis_d
+        cruise_d = move.cruise_r * axis_d
+        decel_d = move.decel_r * axis_d
+
+        retract_t = retract_d = retract_v = 0.
+        decel_v = cruise_v
+
+        # Update for pressure advance
+        start_pos = self.extrude_pos
+        if (axis_d >= 0. and (move.axes_d[0] or move.axes_d[1])
+            and self.pressure_advance):
+            # Increase accel_d and start_v when accelerating
+            move_extrude_r = move.extrude_r
+            prev_pressure_d = start_pos - move.start_pos[3]
+            if accel_t:
+                npd = move.cruise_v * move_extrude_r * self.pressure_advance
+                extra_accel_d = npd - prev_pressure_d
+                if extra_accel_d > 0.:
+                    accel_d += extra_accel_d
+                    start_v += extra_accel_d / accel_t
+                    prev_pressure_d += extra_accel_d
+            # Update decel and retract parameters when decelerating
+            if decel_t:
+                if move.corner_min:
+                    npd = move.corner_max*move_extrude_r * self.pressure_advance
+                    extra_decel_d = prev_pressure_d - npd
+                    if move.end_v > move.corner_min:
+                        extra_decel_d *= ((move.cruise_v - move.end_v)
+                                          / (move.cruise_v - move.corner_min))
+                else:
+                    npd = move.end_v * move_extrude_r * self.pressure_advance
+                    extra_decel_d = prev_pressure_d - npd
+                if extra_decel_d > 0.:
+                    extra_decel_v = extra_decel_d / decel_t
+                    decel_v -= extra_decel_v
+                    end_v -= extra_decel_v
+                    if decel_v <= 0.:
+                        # The entire decel phase is replaced with retraction
+                        retract_t = decel_t
+                        retract_d = -(end_v + decel_v) * 0.5 * decel_t
+                        retract_v = -decel_v
+                        decel_t = decel_d = 0.
+                    elif end_v < 0.:
+                        # Split decel phase into decel and retraction
+                        retract_t = -end_v * inv_accel
+                        retract_d = -end_v * 0.5 * retract_t
+                        decel_t -= retract_t
+                        decel_d = decel_v * 0.5 * decel_t
+                    else:
+                        # There is still only a decel phase (no retraction)
+                        decel_d -= extra_decel_d
+
+        # Prepare for steps
+        inv_step_dist = self.stepper.inv_step_dist
+        step_dist = self.stepper.step_dist
+        mcu_stepper = self.stepper.mcu_stepper
+        mcu_time = mcu_stepper.print_to_mcu_time(move_time)
+        step_pos = mcu_stepper.commanded_position
+        step_offset = step_pos - start_pos * inv_step_dist
+
+        # Acceleration steps
+        accel_multiplier = 2.0 * step_dist * inv_accel
+        if accel_d:
+            #t = sqrt(2*pos/accel + (start_v/accel)**2) - start_v/accel
+            accel_time_offset = start_v * inv_accel
+            accel_sqrt_offset = accel_time_offset**2
+            accel_steps = accel_d * inv_step_dist
+            count = mcu_stepper.step_sqrt(
+                mcu_time - accel_time_offset, accel_steps, step_offset
+                , accel_sqrt_offset, accel_multiplier)
+            step_offset += count - accel_steps
+            mcu_time += accel_t
+        # Cruising steps
+        if cruise_d:
+            #t = pos/cruise_v
+            cruise_multiplier = step_dist / cruise_v
+            cruise_steps = cruise_d * inv_step_dist
+            count = mcu_stepper.step_factor(
+                mcu_time, cruise_steps, step_offset, cruise_multiplier)
+            step_offset += count - cruise_steps
+            mcu_time += cruise_t
+        # Deceleration steps
+        if decel_d:
+            #t = cruise_v/accel - sqrt((cruise_v/accel)**2 - 2*pos/accel)
+            decel_time_offset = decel_v * inv_accel
+            decel_sqrt_offset = decel_time_offset**2
+            decel_steps = decel_d * inv_step_dist
+            count = mcu_stepper.step_sqrt(
+                mcu_time + decel_time_offset, decel_steps, step_offset
+                , decel_sqrt_offset, -accel_multiplier)
+            step_offset += count - decel_steps
+            mcu_time += decel_t
+        # Retraction steps
+        if retract_d:
+            #t = sqrt(2*pos/accel + (start_v/accel)**2) - start_v/accel
+            accel_time_offset = retract_v * inv_accel
+            accel_sqrt_offset = accel_time_offset**2
+            accel_steps = -retract_d * inv_step_dist
+            count = mcu_stepper.step_sqrt(
+                mcu_time - accel_time_offset, accel_steps, step_offset
+                , accel_sqrt_offset, accel_multiplier)
+
+        self.extrude_pos = start_pos + accel_d + cruise_d + decel_d - retract_d

klippy/fan.py

@@ -0,0 +1,35 @@
+# Printer fan support
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+
+FAN_MIN_TIME = 0.1
+
+class PrinterFan:
+    def __init__(self, printer, config):
+        self.printer = printer
+        self.config = config
+        self.mcu_fan = None
+        self.last_fan_value = 0
+        self.last_fan_time = 0.
+        self.kick_start_time = config.getfloat('kick_start_time', 0.1)
+    def build_config(self):
+        pin = self.config.get('pin')
+        hard_pwm = self.config.getint('hard_pwm', 128)
+        self.mcu_fan = self.printer.mcu.create_pwm(pin, hard_pwm, 0)
+    # External commands
+    def set_speed(self, print_time, value):
+        value = max(0, min(255, int(value*255. + 0.5)))
+        if value == self.last_fan_value:
+            return
+        mcu_time = self.mcu_fan.print_to_mcu_time(print_time)
+        mcu_time = max(self.last_fan_time + FAN_MIN_TIME, mcu_time)
+        if (value and value < 255
+            and not self.last_fan_value and self.kick_start_time):
+            # Run fan at full speed for specified kick_start_time
+            self.mcu_fan.set_pwm(mcu_time, 255)
+            mcu_time += self.kick_start_time
+        self.mcu_fan.set_pwm(mcu_time, value)
+        self.last_fan_time = mcu_time
+        self.last_fan_value = value

klippy/gcode.py

@@ -0,0 +1,378 @@
+# Parse gcode commands
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import os, re, logging, collections, time
+import homing
+
+# Parse out incoming GCode and find and translate head movements
+class GCodeParser:
+    RETRY_TIME = 0.100
+    def __init__(self, printer, fd, is_fileinput=False):
+        self.printer = printer
+        self.fd = fd
+        self.is_fileinput = is_fileinput
+        # Input handling
+        self.reactor = printer.reactor
+        self.is_processing_data = False
+        self.fd_handle = None
+        if not is_fileinput:
+            self.fd_handle = self.reactor.register_fd(self.fd, self.process_data)
+        self.input_commands = [""]
+        self.bytes_read = 0
+        self.input_log = collections.deque([], 50)
+        # Command handling
+        self.gcode_handlers = {}
+        self.is_printer_ready = False
+        self.need_ack = False
+        self.toolhead = self.heater_nozzle = self.heater_bed = self.fan = None
+        self.speed = 25.0
+        self.absolutecoord = self.absoluteextrude = True
+        self.base_position = [0.0, 0.0, 0.0, 0.0]
+        self.last_position = [0.0, 0.0, 0.0, 0.0]
+        self.homing_add = [0.0, 0.0, 0.0, 0.0]
+        self.axis2pos = {'X': 0, 'Y': 1, 'Z': 2, 'E': 3}
+        self.build_handlers()
+    def build_config(self):
+        self.toolhead = self.printer.objects['toolhead']
+        self.heater_nozzle = None
+        extruder = self.printer.objects.get('extruder')
+        if extruder:
+            self.heater_nozzle = extruder.heater
+        self.heater_bed = self.printer.objects.get('heater_bed')
+        self.fan = self.printer.objects.get('fan')
+    def build_handlers(self):
+        handlers = ['G1', 'G4', 'G20', 'G21', 'G28', 'G90', 'G91', 'G92',
+                    'M18', 'M82', 'M83', 'M105', 'M110', 'M112', 'M114', 'M206',
+                    'HELP', 'QUERY_ENDSTOPS', 'RESTART', 'CLEAR_SHUTDOWN',
+                    'STATUS']
+        if self.heater_nozzle is not None:
+            handlers.extend(['M104', 'M109', 'PID_TUNE'])
+        if self.heater_bed is not None:
+            handlers.extend(['M140', 'M190'])
+        if self.fan is not None:
+            handlers.extend(['M106', 'M107'])
+        if not self.is_printer_ready:
+            handlers = [h for h in handlers
+                        if getattr(self, 'cmd_'+h+'_when_not_ready', False)]
+        self.gcode_handlers = dict((h, getattr(self, 'cmd_'+h))
+                                   for h in handlers)
+        for h, f in self.gcode_handlers.items():
+            aliases = getattr(self, 'cmd_'+h+'_aliases', [])
+            self.gcode_handlers.update(dict([(a, f) for a in aliases]))
+    def stats(self, eventtime):
+        return "gcodein=%d" % (self.bytes_read,)
+    def set_printer_ready(self, is_ready):
+        if self.is_printer_ready == is_ready:
+            return
+        self.is_printer_ready = is_ready
+        self.build_handlers()
+        if is_ready and self.is_fileinput and self.fd_handle is None:
+            self.fd_handle = self.reactor.register_fd(self.fd, self.process_data)
+    def motor_heater_off(self):
+        if self.toolhead is not None:
+            self.toolhead.motor_off()
+        if self.heater_nozzle is not None:
+            self.heater_nozzle.set_temp(0., 0.)
+        if self.heater_bed is not None:
+            self.heater_bed.set_temp(0., 0.)
+    def dump_debug(self):
+        logging.info("Dumping gcode input %d blocks" % (
+            len(self.input_log),))
+        for eventtime, data in self.input_log:
+            logging.info("Read %f: %s" % (eventtime, repr(data)))
+    # Parse input into commands
+    args_r = re.compile('([a-zA-Z_]+|[a-zA-Z*])')
+    def process_commands(self, eventtime):
+        while len(self.input_commands) > 1:
+            line = self.input_commands.pop(0)
+            # Ignore comments and leading/trailing spaces
+            line = origline = line.strip()
+            cpos = line.find(';')
+            if cpos >= 0:
+                line = line[:cpos]
+            # Break command into parts
+            parts = self.args_r.split(line)[1:]
+            params = dict((parts[i].upper(), parts[i+1].strip())
+                          for i in range(0, len(parts), 2))
+            params['#original'] = origline
+            if parts and parts[0].upper() == 'N':
+                # Skip line number at start of command
+                del parts[:2]
+            if not parts:
+                self.cmd_default(params)
+                continue
+            params['#command'] = cmd = parts[0].upper() + parts[1].strip()
+            # Invoke handler for command
+            self.need_ack = True
+            handler = self.gcode_handlers.get(cmd, self.cmd_default)
+            try:
+                handler(params)
+            except:
+                logging.exception("Exception in command handler")
+                self.toolhead.force_shutdown()
+                self.respond_error('Internal error on command:"%s"' % (cmd,))
+            self.ack()
+    def process_data(self, eventtime):
+        data = os.read(self.fd, 4096)
+        self.input_log.append((eventtime, data))
+        self.bytes_read += len(data)
+        lines = data.split('\n')
+        lines[0] = self.input_commands.pop() + lines[0]
+        self.input_commands.extend(lines)
+        if self.is_processing_data:
+            if len(lines) <= 1:
+                return
+            if not self.is_fileinput and lines[0].strip().upper() == 'M112':
+                self.cmd_M112({})
+            self.reactor.unregister_fd(self.fd_handle)
+            self.fd_handle = None
+            return
+        self.is_processing_data = True
+        self.process_commands(eventtime)
+        self.is_processing_data = False
+        if self.fd_handle is None:
+            self.fd_handle = self.reactor.register_fd(self.fd, self.process_data)
+        if not data and self.is_fileinput:
+            self.motor_heater_off()
+            self.printer.request_exit_eof()
+    # Response handling
+    def ack(self, msg=None):
+        if not self.need_ack or self.is_fileinput:
+            return
+        if msg:
+            os.write(self.fd, "ok %s\n" % (msg,))
+        else:
+            os.write(self.fd, "ok\n")
+        self.need_ack = False
+    def respond(self, msg):
+        logging.debug(msg)
+        if self.is_fileinput:
+            return
+        os.write(self.fd, msg+"\n")
+    def respond_info(self, msg):
+        lines = [l.strip() for l in msg.strip().split('\n')]
+        self.respond("// " + "\n// ".join(lines))
+    def respond_error(self, msg):
+        lines = msg.strip().split('\n')
+        if len(lines) > 1:
+            self.respond_info("\n".join(lines[:-1]))
+        self.respond('!! %s' % (lines[-1].strip(),))
+    # Temperature wrappers
+    def get_temp(self):
+        if not self.is_printer_ready:
+            return "T:0"
+        # T:XXX /YYY B:XXX /YYY
+        out = []
+        if self.heater_nozzle:
+            cur, target = self.heater_nozzle.get_temp()
+            out.append("T:%.1f /%.1f" % (cur, target))
+        if self.heater_bed:
+            cur, target = self.heater_bed.get_temp()
+            out.append("B:%.1f /%.1f" % (cur, target))
+        return " ".join(out)
+    def bg_temp(self, heater):
+        if self.is_fileinput:
+            return
+        eventtime = time.time()
+        while self.is_printer_ready and heater.check_busy(eventtime):
+            self.toolhead.reset_motor_off_time(eventtime)
+            self.respond(self.get_temp())
+            eventtime = self.reactor.pause(eventtime + 1.)
+    def set_temp(self, heater, params, wait=False):
+        print_time = self.toolhead.get_last_move_time()
+        temp = float(params.get('S', '0'))
+        heater.set_temp(print_time, temp)
+        if wait:
+            self.bg_temp(heater)
+    # Individual command handlers
+    def cmd_default(self, params):
+        if not self.is_printer_ready:
+            self.respond_error(self.printer.get_state_message())
+            return
+        cmd = params.get('#command')
+        if not cmd:
+            logging.debug(params['#original'])
+            return
+        self.respond('echo:Unknown command:"%s"' % (cmd,))
+    cmd_G1_aliases = ['G0']
+    def cmd_G1(self, params):
+        # Move
+        for a, p in self.axis2pos.items():
+            if a in params:
+                v = float(params[a])
+                if not self.absolutecoord or (p>2 and not self.absoluteextrude):
+                    # value relative to position of last move
+                    self.last_position[p] += v
+                else:
+                    # value relative to base coordinate position
+                    self.last_position[p] = v + self.base_position[p]
+        if 'F' in params:
+            self.speed = float(params['F']) / 60.
+        try:
+            self.toolhead.move(self.last_position, self.speed)
+        except homing.EndstopError, e:
+            self.respond_error(str(e))
+            self.last_position = self.toolhead.get_position()
+    def cmd_G4(self, params):
+        # Dwell
+        if 'S' in params:
+            delay = float(params['S'])
+        else:
+            delay = float(params.get('P', '0')) / 1000.
+        self.toolhead.dwell(delay)
+    def cmd_G20(self, params):
+        # Set units to inches
+        self.respond_error('Machine does not support G20 (inches) command')
+    def cmd_G21(self, params):
+        # Set units to millimeters
+        pass
+    def cmd_G28(self, params):
+        # Move to origin
+        axes = []
+        for axis in 'XYZ':
+            if axis in params:
+                axes.append(self.axis2pos[axis])
+        if not axes:
+            axes = [0, 1, 2]
+        homing_state = homing.Homing(self.toolhead, axes)
+        if self.is_fileinput:
+            homing_state.set_no_verify_retract()
+        try:
+            self.toolhead.home(homing_state)
+        except homing.EndstopError, e:
+            self.toolhead.motor_off()
+            self.respond_error(str(e))
+            return
+        newpos = self.toolhead.get_position()
+        for axis in homing_state.get_axes():
+            self.last_position[axis] = newpos[axis]
+            self.base_position[axis] = -self.homing_add[axis]
+    def cmd_G90(self, params):
+        # Use absolute coordinates
+        self.absolutecoord = True
+    def cmd_G91(self, params):
+        # Use relative coordinates
+        self.absolutecoord = False
+    def cmd_G92(self, params):
+        # Set position
+        mcount = 0
+        for a, p in self.axis2pos.items():
+            if a in params:
+                self.base_position[p] = self.last_position[p] - float(params[a])
+                mcount += 1
+        if not mcount:
+            self.base_position = list(self.last_position)
+    def cmd_M82(self, params):
+        # Use absolute distances for extrusion
+        self.absoluteextrude = True
+    def cmd_M83(self, params):
+        # Use relative distances for extrusion
+        self.absoluteextrude = False
+    cmd_M18_aliases = ["M84"]
+    def cmd_M18(self, params):
+        # Turn off motors
+        self.toolhead.motor_off()
+    cmd_M105_when_not_ready = True
+    def cmd_M105(self, params):
+        # Get Extruder Temperature
+        self.ack(self.get_temp())
+    def cmd_M104(self, params):
+        # Set Extruder Temperature
+        self.set_temp(self.heater_nozzle, params)
+    def cmd_M109(self, params):
+        # Set Extruder Temperature and Wait
+        self.set_temp(self.heater_nozzle, params, wait=True)
+    cmd_M110_when_not_ready = True
+    def cmd_M110(self, params):
+        # Set Current Line Number
+        pass
+    def cmd_M112(self, params):
+        # Emergency Stop
+        self.toolhead.force_shutdown()
+    cmd_M114_when_not_ready = True
+    def cmd_M114(self, params):
+        # Get Current Position
+        if self.toolhead is None:
+            self.cmd_default(params)
+            return
+        kinpos = self.toolhead.get_position()
+        self.respond("X:%.3f Y:%.3f Z:%.3f E:%.3f Count X:%.3f Y:%.3f Z:%.3f" % (
+            self.last_position[0], self.last_position[1],
+            self.last_position[2], self.last_position[3],
+            kinpos[0], kinpos[1], kinpos[2]))
+    def cmd_M140(self, params):
+        # Set Bed Temperature
+        self.set_temp(self.heater_bed, params)
+    def cmd_M190(self, params):
+        # Set Bed Temperature and Wait
+        self.set_temp(self.heater_bed, params, wait=True)
+    def cmd_M106(self, params):
+        # Set fan speed
+        print_time = self.toolhead.get_last_move_time()
+        self.fan.set_speed(print_time, float(params.get('S', '255')) / 255.)
+    def cmd_M107(self, params):
+        # Turn fan off
+        print_time = self.toolhead.get_last_move_time()
+        self.fan.set_speed(print_time, 0)
+    def cmd_M206(self, params):
+        # Set home offset
+        for a, p in self.axis2pos.items():
+            if a in params:
+                v = float(params[a])
+                self.base_position[p] += self.homing_add[p] - v
+                self.homing_add[p] = v
+    cmd_QUERY_ENDSTOPS_help = "Report on the status of each endstop"
+    cmd_QUERY_ENDSTOPS_aliases = ["M119"]
+    def cmd_QUERY_ENDSTOPS(self, params):
+        # Get Endstop Status
+        if self.is_fileinput:
+            return
+        try:
+            res = self.toolhead.query_endstops()
+        except self.printer.mcu.error, e:
+            self.respond_error(str(e))
+            return
+        self.respond(" ".join(["%s:%s" % (name, ["open", "TRIGGERED"][not not t])
+                               for name, t in res]))
+    cmd_PID_TUNE_help = "Run PID Tuning"
+    cmd_PID_TUNE_aliases = ["M303"]
+    def cmd_PID_TUNE(self, params):
+        # Run PID tuning
+        heater = int(params.get('E', '0'))
+        heater = {0: self.heater_nozzle, -1: self.heater_bed}[heater]
+        temp = float(params.get('S', '60'))
+        heater.start_auto_tune(temp)
+        self.bg_temp(heater)
+    cmd_CLEAR_SHUTDOWN_when_not_ready = True
+    cmd_CLEAR_SHUTDOWN_help = "Clear a firmware shutdown and restart"
+    def cmd_CLEAR_SHUTDOWN(self, params):
+        if self.toolhead is None:
+            self.cmd_default(params)
+            return
+        self.printer.mcu.clear_shutdown()
+        self.printer.request_restart()
+    cmd_RESTART_when_not_ready = True
+    cmd_RESTART_help = "Reload config file and restart host software"
+    def cmd_RESTART(self, params):
+        self.printer.request_restart()
+    cmd_STATUS_when_not_ready = True
+    cmd_STATUS_help = "Report the printer status"
+    def cmd_STATUS(self, params):
+        msg = self.printer.get_state_message()
+        if self.is_printer_ready:
+            self.respond_info(msg)
+        else:
+            self.respond_error(msg)
+    cmd_HELP_when_not_ready = True
+    def cmd_HELP(self, params):
+        cmdhelp = []
+        if not self.is_printer_ready:
+            cmdhelp.append("Printer is not ready - not all commands available.")
+        cmdhelp.append("Available extended commands:")
+        for cmd in self.gcode_handlers:
+            desc = getattr(self, 'cmd_'+cmd+'_help', None)
+            if desc is not None:
+                cmdhelp.append("%-10s: %s" % (cmd, desc))
+        self.respond_info("\n".join(cmdhelp))

klippy/heater.py

@@ -0,0 +1,280 @@
+# Printer heater support
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import math, logging, threading
+
+# Mapping from name to Steinhart-Hart coefficients
+Thermistors = {
+    "EPCOS 100K B57560G104F": (
+        0.000722136308968056, 0.000216766566488498, 8.92935804531095e-08),
+    "ATC Semitec 104GT-2": (
+        0.000809651054275124, 0.000211636030735685,  7.07420883993973e-08),
+}
+
+SAMPLE_TIME = 0.001
+SAMPLE_COUNT = 8
+REPORT_TIME = 0.300
+KELVIN_TO_CELCIUS = -273.15
+MAX_HEAT_TIME = 5.0
+AMBIENT_TEMP = 25.
+PWM_MAX = 255
+
+class PrinterHeater:
+    def __init__(self, printer, config):
+        self.printer = printer
+        self.config = config
+        self.mcu_pwm = self.mcu_adc = None
+        self.thermistor_c = config.getchoice('thermistor_type', Thermistors)
+        self.pullup_r = config.getfloat('pullup_resistor', 4700.)
+        self.min_extrude_temp = config.getfloat('min_extrude_temp', 170.)
+        self.can_extrude = (self.min_extrude_temp <= 0.)
+        self.lock = threading.Lock()
+        self.last_temp = 0.
+        self.last_temp_time = 0.
+        self.target_temp = 0.
+        self.control = None
+        # pwm caching
+        self.next_pwm_time = 0.
+        self.last_pwm_value = 0
+    def build_config(self):
+        heater_pin = self.config.get('heater_pin')
+        thermistor_pin = self.config.get('thermistor_pin')
+        self.mcu_pwm = self.printer.mcu.create_pwm(heater_pin, 0, MAX_HEAT_TIME)
+        self.mcu_adc = self.printer.mcu.create_adc(thermistor_pin)
+        min_adc = self.calc_adc(self.config.getfloat('max_temp'))
+        max_adc = self.calc_adc(self.config.getfloat('min_temp'))
+        self.mcu_adc.set_minmax(
+            SAMPLE_TIME, SAMPLE_COUNT, minval=min_adc, maxval=max_adc)
+        self.mcu_adc.set_adc_callback(REPORT_TIME, self.adc_callback)
+        algos = {'watermark': ControlBangBang, 'pid': ControlPID}
+        self.control = self.config.getchoice('control', algos)(self, self.config)
+        if self.printer.mcu.is_fileoutput():
+            self.can_extrude = True
+    def set_pwm(self, read_time, value):
+        if value:
+            if self.target_temp <= 0.:
+                return
+            if (read_time < self.next_pwm_time
+                and abs(value - self.last_pwm_value) < 15):
+                return
+        elif not self.last_pwm_value:
+            return
+        pwm_time = read_time + REPORT_TIME + SAMPLE_TIME*SAMPLE_COUNT
+        self.next_pwm_time = pwm_time + 0.75 * MAX_HEAT_TIME
+        self.last_pwm_value = value
+        logging.debug("pwm=%d@%.3f (%.3f)" % (value, read_time, pwm_time))
+        self.mcu_pwm.set_pwm(pwm_time, value)
+    # Temperature calculation
+    def calc_temp(self, adc):
+        r = self.pullup_r * adc / (1.0 - adc)
+        ln_r = math.log(r)
+        c1, c2, c3 = self.thermistor_c
+        temp_inv = c1 + c2*ln_r + c3*math.pow(ln_r, 3)
+        return 1.0/temp_inv + KELVIN_TO_CELCIUS
+    def calc_adc(self, temp):
+        if temp is None:
+            return None
+        c1, c2, c3 = self.thermistor_c
+        temp -= KELVIN_TO_CELCIUS
+        temp_inv = 1./temp
+        y = (c1 - temp_inv) / (2*c3)
+        x = math.sqrt(math.pow(c2 / (3.*c3), 3.) + math.pow(y, 2.))
+        r = math.exp(math.pow(x-y, 1./3.) - math.pow(x+y, 1./3.))
+        return r / (self.pullup_r + r)
+    def adc_callback(self, read_time, read_value):
+        temp = self.calc_temp(read_value)
+        with self.lock:
+            self.last_temp = temp
+            self.last_temp_time = read_time
+            self.can_extrude = (temp >= self.min_extrude_temp)
+            self.control.adc_callback(read_time, temp)
+        #logging.debug("temp: %.3f %f = %f" % (read_time, read_value, temp))
+    # External commands
+    def set_temp(self, print_time, degrees):
+        with self.lock:
+            self.target_temp = degrees
+    def get_temp(self):
+        with self.lock:
+            return self.last_temp, self.target_temp
+    def check_busy(self, eventtime):
+        with self.lock:
+            return self.control.check_busy(eventtime)
+    def start_auto_tune(self, temp):
+        with self.lock:
+            self.control = ControlAutoTune(self, self.control, temp)
+
+
+######################################################################
+# Bang-bang control algo
+######################################################################
+
+class ControlBangBang:
+    def __init__(self, heater, config):
+        self.heater = heater
+        self.max_delta = config.getfloat('max_delta', 2.0)
+        self.heating = False
+    def adc_callback(self, read_time, temp):
+        if self.heating and temp >= self.heater.target_temp+self.max_delta:
+            self.heating = False
+        elif not self.heating and temp <= self.heater.target_temp-self.max_delta:
+            self.heating = True
+        if self.heating:
+            self.heater.set_pwm(read_time, PWM_MAX)
+        else:
+            self.heater.set_pwm(read_time, 0)
+    def check_busy(self, eventtime):
+        return self.heater.last_temp < self.heater.target_temp-self.max_delta
+
+
+######################################################################
+# Proportional Integral Derivative (PID) control algo
+######################################################################
+
+class ControlPID:
+    def __init__(self, heater, config):
+        self.heater = heater
+        self.Kp = config.getfloat('pid_Kp')
+        self.Ki = config.getfloat('pid_Ki')
+        self.Kd = config.getfloat('pid_Kd')
+        self.min_deriv_time = config.getfloat('pid_deriv_time', 2.)
+        imax = config.getint('pid_integral_max', PWM_MAX)
+        self.temp_integ_max = imax / self.Ki
+        self.prev_temp = AMBIENT_TEMP
+        self.prev_temp_time = 0.
+        self.prev_temp_deriv = 0.
+        self.prev_temp_integ = 0.
+    def adc_callback(self, read_time, temp):
+        time_diff = read_time - self.prev_temp_time
+        # Calculate change of temperature
+        temp_diff = temp - self.prev_temp
+        if time_diff >= self.min_deriv_time:
+            temp_deriv = temp_diff / time_diff
+        else:
+            temp_deriv = (self.prev_temp_deriv * (self.min_deriv_time-time_diff)
+                          + temp_diff) / self.min_deriv_time
+        # Calculate accumulated temperature "error"
+        temp_err = self.heater.target_temp - temp
+        temp_integ = self.prev_temp_integ + temp_err * time_diff
+        temp_integ = max(0., min(self.temp_integ_max, temp_integ))
+        # Calculate output
+        co = int(self.Kp*temp_err + self.Ki*temp_integ - self.Kd*temp_deriv)
+        #logging.debug("pid: %f@%.3f -> diff=%f deriv=%f err=%f integ=%f co=%d" % (
+        #    temp, read_time, temp_diff, temp_deriv, temp_err, temp_integ, co))
+        bounded_co = max(0, min(PWM_MAX, co))
+        self.heater.set_pwm(read_time, bounded_co)
+        # Store state for next measurement
+        self.prev_temp = temp
+        self.prev_temp_time = read_time
+        self.prev_temp_deriv = temp_deriv
+        if co == bounded_co:
+            self.prev_temp_integ = temp_integ
+    def check_busy(self, eventtime):
+        temp_diff = self.heater.target_temp - self.heater.last_temp
+        return abs(temp_diff) > 1. or abs(self.prev_temp_deriv) > 0.1
+
+
+######################################################################
+# Ziegler-Nichols PID autotuning
+######################################################################
+
+TUNE_PID_DELTA = 5.0
+
+class ControlAutoTune:
+    def __init__(self, heater, old_control, target_temp):
+        self.heater = heater
+        self.old_control = old_control
+        self.target_temp = target_temp
+        self.heating = False
+        self.peaks = []
+        self.peak = 0.
+        self.peak_time = 0.
+    def adc_callback(self, read_time, temp):
+        if self.heating and temp >= self.target_temp:
+            self.heating = False
+            self.check_peaks()
+        elif not self.heating and temp <= self.target_temp - TUNE_PID_DELTA:
+            self.heating = True
+            self.check_peaks()
+        if self.heating:
+            self.heater.set_pwm(read_time, PWM_MAX)
+            if temp < self.peak:
+                self.peak = temp
+                self.peak_time = read_time
+        else:
+            self.heater.set_pwm(read_time, 0)
+            if temp > self.peak:
+                self.peak = temp
+                self.peak_time = read_time
+    def check_peaks(self):
+        self.peaks.append((self.peak, self.peak_time))
+        if self.heating:
+            self.peak = 9999999.
+        else:
+            self.peak = -9999999.
+        if len(self.peaks) < 4:
+            return
+        temp_diff = self.peaks[-1][0] - self.peaks[-2][0]
+        time_diff = self.peaks[-1][1] - self.peaks[-3][1]
+        pwm_diff = PWM_MAX - 0
+        Ku = 4. * (2. * pwm_diff) / (abs(temp_diff) * math.pi)
+        Tu = time_diff
+
+        Kp = 0.6 * Ku
+        Ti = 0.5 * Tu
+        Td = 0.125 * Tu
+        Ki = Kp / Ti
+        Kd = Kp * Td
+        logging.info("Autotune: raw=%f/%d Ku=%f Tu=%f  Kp=%f Ki=%f Kd=%f" % (
+            temp_diff, pwm_diff, Ku, Tu, Kp, Ki, Kd))
+    def check_busy(self, eventtime):
+        if self.heating or len(self.peaks) < 12:
+            return True
+        self.heater.control = self.old_control
+        return False
+
+
+######################################################################
+# Tuning information test
+######################################################################
+
+class ControlBumpTest:
+    def __init__(self, heater, old_control, target_temp):
+        self.heater = heater
+        self.old_control = old_control
+        self.target_temp = target_temp
+        self.temp_samples = {}
+        self.pwm_samples = {}
+        self.state = 0
+    def set_pwm(self, read_time, value):
+        self.pwm_samples[read_time + 2*REPORT_TIME] = value
+        self.heater.set_pwm(read_time, value)
+    def adc_callback(self, read_time, temp):
+        self.temp_samples[read_time] = temp
+        if not self.state:
+            self.set_pwm(read_time, 0)
+            if len(self.temp_samples) >= 20:
+                self.state += 1
+        elif self.state == 1:
+            if temp < self.target_temp:
+                self.set_pwm(read_time, PWM_MAX)
+                return
+            self.set_pwm(read_time, 0)
+            self.state += 1
+        elif self.state == 2:
+            self.set_pwm(read_time, 0)
+            if temp <= (self.target_temp + AMBIENT_TEMP) / 2.:
+                self.dump_stats()
+                self.state += 1
+    def dump_stats(self):
+        out = ["%.3f %.1f %d" % (time, temp, self.pwm_samples.get(time, -1.))
+               for time, temp in sorted(self.temp_samples.items())]
+        f = open("/tmp/heattest.txt", "wb")
+        f.write('\n'.join(out))
+        f.close()
+    def check_busy(self, eventtime):
+        if self.state < 3:
+            return True
+        self.heater.control = self.old_control
+        return False

klippy/homing.py

@@ -0,0 +1,61 @@
+# Code for state tracking during homing operations
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import logging
+
+class Homing:
+    def __init__(self, toolhead, changed_axes):
+        self.toolhead = toolhead
+        self.changed_axes = changed_axes
+        self.verify_retract = True
+    def set_no_verify_retract(self):
+        self.verify_retract = False
+    def set_axes(self, axes):
+        self.changed_axes = axes
+    def get_axes(self):
+        return self.changed_axes
+    def _fill_coord(self, coord):
+        # Fill in any None entries in 'coord' with current toolhead position
+        thcoord = list(self.toolhead.get_position())
+        for i in range(len(coord)):
+            if coord[i] is not None:
+                thcoord[i] = coord[i]
+        return thcoord
+    def retract(self, newpos, speed):
+        self.toolhead.move(self._fill_coord(newpos), speed)
+    def home(self, forcepos, movepos, steppers, speed, second_home=False):
+        # Alter kinematics class to think printer is at forcepos
+        self.toolhead.set_position(self._fill_coord(forcepos))
+        # Start homing and issue move
+        print_time = self.toolhead.get_last_move_time()
+        endstops = []
+        for s in steppers:
+            es = s.enable_endstop_checking(print_time, s.step_dist / speed)
+            endstops.append((s, es, s.mcu_stepper.get_mcu_position()))
+        self.toolhead.move(self._fill_coord(movepos), speed)
+        move_end_print_time = self.toolhead.get_last_move_time()
+        self.toolhead.reset_print_time()
+        for s, es, last_pos in endstops:
+            es.home_finalize(es.print_to_mcu_time(move_end_print_time))
+        # Wait for endstops to trigger
+        for s, es, last_pos in endstops:
+            try:
+                es.home_wait()
+            except es.error, e:
+                raise EndstopError("Failed to home stepper %s: %s" % (
+                    s.name, str(e)))
+            post_home_pos = s.mcu_stepper.get_mcu_position()
+            if second_home and self.verify_retract and last_pos == post_home_pos:
+                raise EndstopError("Endstop %s still triggered after retract" % (
+                    s.name,))
+    def set_homed_position(self, pos):
+        self.toolhead.set_position(self._fill_coord(pos))
+
+class EndstopError(Exception):
+    pass
+
+def EndstopMoveError(pos, msg="Move out of range"):
+    return EndstopError("%s: %.3f %.3f %.3f [%.3f]" % (
+            msg, pos[0], pos[1], pos[2], pos[3]))

klippy/klippy.py

@@ -0,0 +1,275 @@
+#!/usr/bin/env python
+# Main code for host side printer firmware
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import sys, optparse, ConfigParser, logging, time, threading
+import gcode, toolhead, util, mcu, fan, heater, extruder, reactor, queuelogger
+
+message_startup = """
+The klippy host software is attempting to connect.  Please
+retry in a few moments.
+Printer is not ready
+"""
+
+message_restart = """
+Once the underlying issue is corrected, use the "RESTART"
+command to reload the config and restart the host software.
+Printer is halted
+"""
+
+message_mcu_connect_error = """
+This is an unrecoverable error.  Please manually restart the
+micro-controller and then issue the "RESTART" command to
+restart the host software.
+Error configuring printer
+"""
+
+message_shutdown = """
+Once the underlying issue is corrected, the "CLEAR_SHUTDOWN"
+command can be used to clear the firmware flag and restart
+the host software.
+Printer is shutdown
+"""
+
+class ConfigWrapper:
+    error = ConfigParser.Error
+    class sentinel:
+        pass
+    def __init__(self, printer, section):
+        self.printer = printer
+        self.section = section
+    def get_wrapper(self, parser, option, default):
+        if (default is not self.sentinel
+            and not self.printer.fileconfig.has_option(self.section, option)):
+            return default
+        self.printer.all_config_options[
+            (self.section.lower(), option.lower())] = 1
+        try:
+            return parser(self.section, option)
+        except self.error, e:
+            raise
+        except:
+            raise self.error("Unable to parse option '%s' in section '%s'" % (
+                option, self.section))
+    def get(self, option, default=sentinel):
+        return self.get_wrapper(self.printer.fileconfig.get, option, default)
+    def getint(self, option, default=sentinel):
+        return self.get_wrapper(self.printer.fileconfig.getint, option, default)
+    def getfloat(self, option, default=sentinel):
+        return self.get_wrapper(
+            self.printer.fileconfig.getfloat, option, default)
+    def getboolean(self, option, default=sentinel):
+        return self.get_wrapper(
+            self.printer.fileconfig.getboolean, option, default)
+    def getchoice(self, option, choices, default=sentinel):
+        c = self.get(option, default)
+        if c not in choices:
+            raise self.error(
+                "Option '%s' in section '%s' is not a valid choice" % (
+                    option, self.section))
+        return choices[c]
+    def getsection(self, section):
+        return ConfigWrapper(self.printer, section)
+
+class Printer:
+    def __init__(self, conffile, input_fd, is_fileinput=False):
+        self.conffile = conffile
+        self.reactor = reactor.Reactor()
+        self.gcode = gcode.GCodeParser(self, input_fd, is_fileinput)
+        self.stats_timer = self.reactor.register_timer(self.stats)
+        self.connect_timer = self.reactor.register_timer(
+            self.connect, self.reactor.NOW)
+        self.all_config_options = {}
+        self.need_dump_debug = False
+        self.state_message = message_startup
+        self.debugoutput = self.dictionary = None
+        self.run_result = None
+        self.fileconfig = None
+        self.mcu = None
+        self.objects = {}
+    def set_fileoutput(self, debugoutput, dictionary):
+        self.debugoutput = debugoutput
+        self.dictionary = dictionary
+    def stats(self, eventtime):
+        if self.need_dump_debug:
+            # Call dump_debug here so it is executed in the main thread
+            self.gcode.dump_debug()
+            self.need_dump_debug = False
+        out = []
+        out.append(self.gcode.stats(eventtime))
+        toolhead = self.objects.get('toolhead')
+        if toolhead is not None:
+            out.append(toolhead.stats(eventtime))
+        if self.mcu is not None:
+            out.append(self.mcu.stats(eventtime))
+        logging.info("Stats %.0f: %s" % (eventtime, ' '.join(out)))
+        return eventtime + 1.
+    def load_config(self):
+        self.fileconfig = ConfigParser.RawConfigParser()
+        res = self.fileconfig.read(self.conffile)
+        if not res:
+            raise ConfigParser.Error("Unable to open config file %s" % (
+                self.conffile,))
+        self.mcu = mcu.MCU(self, ConfigWrapper(self, 'mcu'))
+        if self.fileconfig.has_section('fan'):
+            self.objects['fan'] = fan.PrinterFan(
+                self, ConfigWrapper(self, 'fan'))
+        if self.fileconfig.has_section('extruder'):
+            self.objects['extruder'] = extruder.PrinterExtruder(
+                self, ConfigWrapper(self, 'extruder'))
+        if self.fileconfig.has_section('heater_bed'):
+            self.objects['heater_bed'] = heater.PrinterHeater(
+                self, ConfigWrapper(self, 'heater_bed'))
+        self.objects['toolhead'] = toolhead.ToolHead(
+            self, ConfigWrapper(self, 'printer'))
+    def build_config(self):
+        for oname in sorted(self.objects.keys()):
+            self.objects[oname].build_config()
+        self.gcode.build_config()
+        self.mcu.build_config()
+    def validate_config(self):
+        valid_sections = dict([(s, 1) for s, o in self.all_config_options])
+        for section in self.fileconfig.sections():
+            section = section.lower()
+            if section not in valid_sections:
+                raise ConfigParser.Error("Unknown config file section '%s'" % (
+                    section,))
+            for option in self.fileconfig.options(section):
+                option = option.lower()
+                if (section, option) not in self.all_config_options:
+                    raise ConfigParser.Error(
+                        "Unknown option '%s' in section '%s'" % (
+                            option, section))
+    def connect(self, eventtime):
+        try:
+            self.load_config()
+            if self.debugoutput is None:
+                self.reactor.update_timer(self.stats_timer, self.reactor.NOW)
+            else:
+                self.mcu.connect_file(self.debugoutput, self.dictionary)
+            self.mcu.connect()
+            self.build_config()
+            self.validate_config()
+            self.gcode.set_printer_ready(True)
+            self.state_message = "Printer is ready"
+        except ConfigParser.Error, e:
+            logging.exception("Config error")
+            self.state_message = "%s%s" % (str(e), message_restart)
+            self.reactor.update_timer(self.stats_timer, self.reactor.NEVER)
+        except mcu.error, e:
+            logging.exception("MCU error during connect")
+            self.state_message = "%s%s" % (str(e), message_mcu_connect_error)
+            self.reactor.update_timer(self.stats_timer, self.reactor.NEVER)
+        except:
+            logging.exception("Unhandled exception during connect")
+            self.state_message = "Internal error during connect.%s" % (
+                message_restart)
+            self.reactor.update_timer(self.stats_timer, self.reactor.NEVER)
+        self.reactor.unregister_timer(self.connect_timer)
+        return self.reactor.NEVER
+    def run(self):
+        try:
+            self.reactor.run()
+        except:
+            logging.exception("Unhandled exception during run")
+            return
+        return self.run_result
+    def get_state_message(self):
+        return self.state_message
+    def note_shutdown(self, msg):
+        if self.state_message == 'Running':
+            self.need_dump_debug = True
+        self.state_message = "Firmware shutdown: %s%s" % (
+            msg, message_shutdown)
+        self.gcode.set_printer_ready(False)
+    def note_mcu_error(self, msg):
+        self.state_message = "%s%s" % (msg, message_restart)
+        self.gcode.set_printer_ready(False)
+        self.gcode.motor_heater_off()
+    def disconnect(self):
+        try:
+            if self.mcu is not None:
+                self.stats(time.time())
+                self.mcu.disconnect()
+        except:
+            logging.exception("Unhandled exception during disconnect")
+    def request_restart(self):
+        self.run_result = "restart"
+        self.reactor.end()
+    def request_exit_eof(self):
+        self.run_result = "exit_eof"
+        self.reactor.end()
+
+
+######################################################################
+# Startup
+######################################################################
+
+def read_dictionary(filename):
+    dfile = open(filename, 'rb')
+    dictionary = dfile.read()
+    dfile.close()
+    return dictionary
+
+def main():
+    usage = "%prog [options] <config file>"
+    opts = optparse.OptionParser(usage)
+    opts.add_option("-o", "--debugoutput", dest="outputfile",
+                    help="write output to file instead of to serial port")
+    opts.add_option("-i", "--debuginput", dest="inputfile",
+                    help="read commands from file instead of from tty port")
+    opts.add_option("-I", "--input-tty", dest="inputtty", default='/tmp/printer',
+                    help="input tty name (default is /tmp/printer)")
+    opts.add_option("-l", "--logfile", dest="logfile",
+                    help="write log to file instead of stderr")
+    opts.add_option("-v", action="store_true", dest="verbose",
+                    help="enable debug messages")
+    opts.add_option("-d", dest="read_dictionary",
+                    help="file to read for mcu protocol dictionary")
+    options, args = opts.parse_args()
+    if len(args) != 1:
+        opts.error("Incorrect number of arguments")
+    conffile = args[0]
+
+    input_fd = debuginput = debugoutput = bglogger = None
+
+    debuglevel = logging.INFO
+    if options.verbose:
+        debuglevel = logging.DEBUG
+    if options.inputfile:
+        debuginput = open(options.inputfile, 'rb')
+        input_fd = debuginput.fileno()
+    else:
+        input_fd = util.create_pty(options.inputtty)
+    if options.outputfile:
+        debugoutput = open(options.outputfile, 'wb')
+    if options.logfile:
+        bglogger = queuelogger.setup_bg_logging(options.logfile, debuglevel)
+    else:
+        logging.basicConfig(level=debuglevel)
+    logging.info("Starting Klippy...")
+
+    # Start firmware
+    while 1:
+        is_fileinput = debuginput is not None
+        printer = Printer(conffile, input_fd, is_fileinput)
+        if debugoutput:
+            proto_dict = read_dictionary(options.read_dictionary)
+            printer.set_fileoutput(debugoutput, proto_dict)
+        res = printer.run()
+        if res == 'restart':
+            printer.disconnect()
+            time.sleep(1.)
+            logging.info("Restarting printer")
+            continue
+        elif res == 'exit_eof':
+            printer.disconnect()
+        break
+
+    if bglogger is not None:
+        bglogger.stop()
+
+if __name__ == '__main__':
+    main()

klippy/list.h

@@ -0,0 +1,108 @@
+#ifndef __LIST_H
+#define __LIST_H
+
+#define container_of(ptr, type, member) ({                      \
+        const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
+        (type *)( (char *)__mptr - offsetof(type,member) );})
+
+
+/****************************************************************
+ * list - Double linked lists
+ ****************************************************************/
+
+struct list_node {
+    struct list_node *next, *prev;
+};
+
+struct list_head {
+    struct list_node root;
+};
+
+static inline void
+list_init(struct list_head *h)
+{
+    h->root.prev = h->root.next = &h->root;
+}
+
+static inline int
+list_empty(const struct list_head *h)
+{
+    return h->root.next == &h->root;
+}
+
+static inline void
+list_del(struct list_node *n)
+{
+    struct list_node *prev = n->prev;
+    struct list_node *next = n->next;
+    next->prev = prev;
+    prev->next = next;
+}
+
+static inline void
+__list_add(struct list_node *n, struct list_node *prev, struct list_node *next)
+{
+    next->prev = n;
+    n->next = next;
+    n->prev = prev;
+    prev->next = n;
+}
+
+static inline void
+list_add_after(struct list_node *n, struct list_node *prev)
+{
+    __list_add(n, prev, prev->next);
+}
+
+static inline void
+list_add_before(struct list_node *n, struct list_node *next)
+{
+    __list_add(n, next->prev, next);
+}
+
+static inline void
+list_add_head(struct list_node *n, struct list_head *h)
+{
+    list_add_after(n, &h->root);
+}
+
+static inline void
+list_add_tail(struct list_node *n, struct list_head *h)
+{
+    list_add_before(n, &h->root);
+}
+
+static inline void
+list_join_tail(struct list_head *add, struct list_head *h)
+{
+    if (!list_empty(add)) {
+        struct list_node *prev = h->root.prev;
+        struct list_node *next = &h->root;
+        struct list_node *first = add->root.next;
+        struct list_node *last = add->root.prev;
+        first->prev = prev;
+        prev->next = first;
+        last->next = next;
+        next->prev = last;
+    }
+}
+
+#define list_next_entry(pos, member)                            \
+    container_of((pos)->member.next, typeof(*pos), member)
+
+#define list_first_entry(head, type, member)                    \
+    container_of((head)->root.next, type, member)
+
+#define list_for_each_entry(pos, head, member)                  \
+    for (pos = list_first_entry((head), typeof(*pos), member)   \
+         ; &pos->member != &(head)->root                        \
+         ; pos = list_next_entry(pos, member))
+
+#define list_for_each_entry_safe(pos, n, head, member)          \
+    for (pos = list_first_entry((head), typeof(*pos), member)   \
+          , n = list_next_entry(pos, member)                    \
+         ; &pos->member != &(head)->root                        \
+         ; pos = n, n = list_next_entry(n, member))
+
+
+#endif // list.h

klippy/mcu.py

@@ -0,0 +1,530 @@
+# Multi-processor safe interface to micro-controller
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import sys, zlib, logging, time, math
+import serialhdl, pins, chelper
+
+class error(Exception):
+    pass
+
+def parse_pin_extras(pin, can_pullup=False):
+    pullup = invert = 0
+    if can_pullup and pin.startswith('^'):
+        pullup = 1
+        pin = pin[1:].strip()
+    if pin.startswith('!'):
+        invert = 1
+        pin = pin[1:].strip()
+    return pin, pullup, invert
+
+class MCU_stepper:
+    def __init__(self, mcu, step_pin, dir_pin, min_stop_interval, max_error):
+        self._mcu = mcu
+        self._oid = mcu.create_oid()
+        step_pin, pullup, invert_step = parse_pin_extras(step_pin)
+        dir_pin, pullup, self._invert_dir = parse_pin_extras(dir_pin)
+        self._mcu_freq = mcu.get_mcu_freq()
+        min_stop_interval = int(min_stop_interval * self._mcu_freq)
+        max_error = int(max_error * self._mcu_freq)
+        self.commanded_position = 0
+        self._mcu_position_offset = 0
+        mcu.add_config_cmd(
+            "config_stepper oid=%d step_pin=%s dir_pin=%s"
+            " min_stop_interval=%d invert_step=%d" % (
+                self._oid, step_pin, dir_pin, min_stop_interval, invert_step))
+        mcu.register_stepper(self)
+        self._step_cmd = mcu.lookup_command(
+            "queue_step oid=%c interval=%u count=%hu add=%hi")
+        self._dir_cmd = mcu.lookup_command(
+            "set_next_step_dir oid=%c dir=%c")
+        self._reset_cmd = mcu.lookup_command(
+            "reset_step_clock oid=%c clock=%u")
+        ffi_main, self.ffi_lib = chelper.get_ffi()
+        self._stepqueue = ffi_main.gc(self.ffi_lib.stepcompress_alloc(
+            max_error, self._step_cmd.msgid
+            , self._dir_cmd.msgid, self._invert_dir, self._oid),
+                                      self.ffi_lib.stepcompress_free)
+        self.print_to_mcu_time = mcu.print_to_mcu_time
+    def get_oid(self):
+        return self._oid
+    def get_invert_dir(self):
+        return self._invert_dir
+    def set_position(self, pos):
+        self._mcu_position_offset += self.commanded_position - pos
+        self.commanded_position = pos
+    def set_mcu_position(self, pos):
+        self._mcu_position_offset = pos - self.commanded_position
+    def get_mcu_position(self):
+        return self.commanded_position + self._mcu_position_offset
+    def note_stepper_stop(self):
+        self.ffi_lib.stepcompress_reset(self._stepqueue, 0)
+    def reset_step_clock(self, mcu_time):
+        clock = int(mcu_time * self._mcu_freq)
+        self.ffi_lib.stepcompress_reset(self._stepqueue, clock)
+        data = (self._reset_cmd.msgid, self._oid, clock & 0xffffffff)
+        self.ffi_lib.stepcompress_queue_msg(self._stepqueue, data, len(data))
+    def step(self, mcu_time, sdir):
+        clock = mcu_time * self._mcu_freq
+        self.ffi_lib.stepcompress_push(self._stepqueue, clock, sdir)
+        if sdir:
+            self.commanded_position += 1
+        else:
+            self.commanded_position -= 1
+    def step_sqrt(self, mcu_time, steps, step_offset, sqrt_offset, factor):
+        clock = mcu_time * self._mcu_freq
+        mcu_freq2 = self._mcu_freq**2
+        count = self.ffi_lib.stepcompress_push_sqrt(
+            self._stepqueue, steps, step_offset, clock
+            , sqrt_offset * mcu_freq2, factor * mcu_freq2)
+        self.commanded_position += count
+        return count
+    def step_factor(self, mcu_time, steps, step_offset, factor):
+        clock = mcu_time * self._mcu_freq
+        count = self.ffi_lib.stepcompress_push_factor(
+            self._stepqueue, steps, step_offset, clock, factor * self._mcu_freq)
+        self.commanded_position += count
+        return count
+    def step_delta_const(self, mcu_time, dist, start_pos
+                         , inv_velocity, step_dist
+                         , height, closestxy_d, closest_height2, movez_r):
+        clock = mcu_time * self._mcu_freq
+        count = self.ffi_lib.stepcompress_push_delta_const(
+            self._stepqueue, clock, dist, start_pos
+            , inv_velocity * self._mcu_freq, step_dist
+            , height, closestxy_d, closest_height2, movez_r)
+        self.commanded_position += count
+        return count
+    def step_delta_accel(self, mcu_time, dist, start_pos
+                         , accel_multiplier, step_dist
+                         , height, closestxy_d, closest_height2, movez_r):
+        clock = mcu_time * self._mcu_freq
+        mcu_freq2 = self._mcu_freq**2
+        count = self.ffi_lib.stepcompress_push_delta_accel(
+            self._stepqueue, clock, dist, start_pos
+            , accel_multiplier * mcu_freq2, step_dist
+            , height, closestxy_d, closest_height2, movez_r)
+        self.commanded_position += count
+        return count
+    def get_errors(self):
+        return self.ffi_lib.stepcompress_get_errors(self._stepqueue)
+
+class MCU_endstop:
+    error = error
+    RETRY_QUERY = 1.000
+    def __init__(self, mcu, pin, stepper):
+        self._mcu = mcu
+        self._oid = mcu.create_oid()
+        self._stepper = stepper
+        stepper_oid = stepper.get_oid()
+        pin, pullup, self._invert = parse_pin_extras(pin, can_pullup=True)
+        self._cmd_queue = mcu.alloc_command_queue()
+        mcu.add_config_cmd(
+            "config_end_stop oid=%d pin=%s pull_up=%d stepper_oid=%d" % (
+                self._oid, pin, pullup, stepper_oid))
+        self._home_cmd = mcu.lookup_command(
+            "end_stop_home oid=%c clock=%u rest_ticks=%u pin_value=%c")
+        mcu.register_msg(self._handle_end_stop_state, "end_stop_state"
+                         , self._oid)
+        self._query_cmd = mcu.lookup_command("end_stop_query oid=%c")
+        self._homing = False
+        self._min_query_time = 0.
+        self._next_query_clock = self._home_timeout_clock = 0
+        self._mcu_freq = mcu.get_mcu_freq()
+        self._retry_query_ticks = int(self._mcu_freq * self.RETRY_QUERY)
+        self._last_state = {}
+        self.print_to_mcu_time = mcu.print_to_mcu_time
+    def home_start(self, mcu_time, rest_time):
+        clock = int(mcu_time * self._mcu_freq)
+        rest_ticks = int(rest_time * self._mcu_freq)
+        self._homing = True
+        self._min_query_time = time.time()
+        self._next_query_clock = clock + self._retry_query_ticks
+        msg = self._home_cmd.encode(
+            self._oid, clock, rest_ticks, 1 ^ self._invert)
+        self._mcu.send(msg, reqclock=clock, cq=self._cmd_queue)
+    def home_finalize(self, mcu_time):
+        # XXX - this flushes the serial port of messages ready to be
+        # sent, but doesn't flush messages if they had an unmet minclock
+        self._mcu.serial.send_flush()
+        self._stepper.note_stepper_stop()
+        self._home_timeout_clock = int(mcu_time * self._mcu_freq)
+    def home_wait(self):
+        eventtime = time.time()
+        while self._check_busy(eventtime):
+            eventtime = self._mcu.pause(eventtime + 0.1)
+    def _handle_end_stop_state(self, params):
+        logging.debug("end_stop_state %s" % (params,))
+        self._last_state = params
+    def _check_busy(self, eventtime):
+        # Check if need to send an end_stop_query command
+        if self._mcu.is_fileoutput():
+            return False
+        last_sent_time = self._last_state.get('#sent_time', -1.)
+        if last_sent_time >= self._min_query_time:
+            if not self._homing:
+                return False
+            if not self._last_state.get('homing', 0):
+                pos = self._last_state.get('pos', 0)
+                if self._stepper.get_invert_dir():
+                    pos = -pos
+                self._stepper.set_mcu_position(pos)
+                self._homing = False
+                return False
+            if (self._mcu.serial.get_clock(last_sent_time)
+                > self._home_timeout_clock):
+                # Timeout - disable endstop checking
+                msg = self._home_cmd.encode(self._oid, 0, 0, 0)
+                self._mcu.send(msg, reqclock=0, cq=self._cmd_queue)
+                raise error("Timeout during endstop homing")
+        if self._mcu.is_shutdown:
+            raise error("MCU is shutdown")
+        last_clock, last_clock_time = self._mcu.get_last_clock()
+        if last_clock >= self._next_query_clock:
+            self._next_query_clock = last_clock + self._retry_query_ticks
+            msg = self._query_cmd.encode(self._oid)
+            self._mcu.send(msg, cq=self._cmd_queue)
+        return True
+    def query_endstop(self, mcu_time):
+        clock = int(mcu_time * self._mcu_freq)
+        self._homing = False
+        self._min_query_time = time.time()
+        self._next_query_clock = clock
+    def query_endstop_wait(self):
+        eventtime = time.time()
+        while self._check_busy(eventtime):
+            eventtime = self._mcu.pause(eventtime + 0.1)
+        return self._last_state.get('pin', self._invert) ^ self._invert
+
+class MCU_digital_out:
+    def __init__(self, mcu, pin, max_duration):
+        self._mcu = mcu
+        self._oid = mcu.create_oid()
+        pin, pullup, self._invert = parse_pin_extras(pin)
+        self._last_clock = 0
+        self._last_value = None
+        self._mcu_freq = mcu.get_mcu_freq()
+        self._cmd_queue = mcu.alloc_command_queue()
+        mcu.add_config_cmd(
+            "config_digital_out oid=%d pin=%s default_value=%d"
+            " max_duration=%d" % (self._oid, pin, self._invert, max_duration))
+        self._set_cmd = mcu.lookup_command(
+            "schedule_digital_out oid=%c clock=%u value=%c")
+        self.print_to_mcu_time = mcu.print_to_mcu_time
+    def set_digital(self, mcu_time, value):
+        clock = int(mcu_time * self._mcu_freq)
+        msg = self._set_cmd.encode(self._oid, clock, value ^ self._invert)
+        self._mcu.send(msg, minclock=self._last_clock, reqclock=clock
+                      , cq=self._cmd_queue)
+        self._last_clock = clock
+        self._last_value = value
+    def get_last_setting(self):
+        return self._last_value
+    def set_pwm(self, mcu_time, value):
+        dval = 0
+        if value > 127:
+            dval = 1
+        self.set_digital(mcu_time, dval)
+
+class MCU_pwm:
+    def __init__(self, mcu, pin, cycle_ticks, max_duration, hard_pwm=True):
+        self._mcu = mcu
+        self._oid = mcu.create_oid()
+        self._last_clock = 0
+        self._mcu_freq = mcu.get_mcu_freq()
+        self._cmd_queue = mcu.alloc_command_queue()
+        if hard_pwm:
+            mcu.add_config_cmd(
+                "config_pwm_out oid=%d pin=%s cycle_ticks=%d default_value=0"
+                " max_duration=%d" % (self._oid, pin, cycle_ticks, max_duration))
+            self._set_cmd = mcu.lookup_command(
+                "schedule_pwm_out oid=%c clock=%u value=%c")
+        else:
+            mcu.add_config_cmd(
+                "config_soft_pwm_out oid=%d pin=%s cycle_ticks=%d"
+                " default_value=0 max_duration=%d" % (
+                    self._oid, pin, cycle_ticks, max_duration))
+            self._set_cmd = mcu.lookup_command(
+                "schedule_soft_pwm_out oid=%c clock=%u value=%c")
+        self.print_to_mcu_time = mcu.print_to_mcu_time
+    def set_pwm(self, mcu_time, value):
+        clock = int(mcu_time * self._mcu_freq)
+        msg = self._set_cmd.encode(self._oid, clock, value)
+        self._mcu.send(msg, minclock=self._last_clock, reqclock=clock
+                      , cq=self._cmd_queue)
+        self._last_clock = clock
+
+class MCU_adc:
+    def __init__(self, mcu, pin):
+        self._mcu = mcu
+        self._oid = mcu.create_oid()
+        self._min_sample = 0
+        self._max_sample = 0xffff
+        self._sample_ticks = 0
+        self._sample_count = 1
+        self._report_clock = 0
+        self._callback = None
+        self._inv_max_adc = 0.
+        self._mcu_freq = mcu.get_mcu_freq()
+        self._cmd_queue = mcu.alloc_command_queue()
+        mcu.add_config_cmd("config_analog_in oid=%d pin=%s" % (self._oid, pin))
+        mcu.add_init_callback(self._init_callback)
+        mcu.register_msg(self._handle_analog_in_state, "analog_in_state"
+                         , self._oid)
+        self._query_cmd = mcu.lookup_command(
+            "query_analog_in oid=%c clock=%u sample_ticks=%u sample_count=%c"
+            " rest_ticks=%u min_value=%hu max_value=%hu")
+    def set_minmax(self, sample_time, sample_count, minval=None, maxval=None):
+        self._sample_ticks = int(sample_time * self._mcu_freq)
+        self._sample_count = sample_count
+        if minval is None:
+            minval = 0
+        if maxval is None:
+            maxval = 0xffff
+        mcu_adc_max = float(self._mcu.serial.msgparser.config["ADC_MAX"])
+        max_adc = sample_count * mcu_adc_max
+        self._min_sample = int(minval * max_adc)
+        self._max_sample = min(0xffff, int(math.ceil(maxval * max_adc)))
+        self._inv_max_adc = 1.0 / max_adc
+    def _init_callback(self):
+        last_clock, last_clock_time = self._mcu.get_last_clock()
+        clock = last_clock + int(self._mcu_freq * (1.0 + self._oid * 0.01)) # XXX
+        msg = self._query_cmd.encode(
+            self._oid, clock, self._sample_ticks, self._sample_count
+            , self._report_clock, self._min_sample, self._max_sample)
+        self._mcu.send(msg, reqclock=clock, cq=self._cmd_queue)
+    def _handle_analog_in_state(self, params):
+        last_value = params['value'] * self._inv_max_adc
+        next_clock = self._mcu.serial.translate_clock(params['next_clock'])
+        last_read_time = (next_clock - self._report_clock) / self._mcu_freq
+        if self._callback is not None:
+            self._callback(last_read_time, last_value)
+    def set_adc_callback(self, report_time, callback):
+        self._report_clock = int(report_time * self._mcu_freq)
+        self._callback = callback
+
+class MCU:
+    error = error
+    COMM_TIMEOUT = 3.5
+    def __init__(self, printer, config):
+        self._printer = printer
+        self._config = config
+        # Serial port
+        baud = config.getint('baud', 115200)
+        serialport = config.get('serial', '/dev/ttyS0')
+        self.serial = serialhdl.SerialReader(printer.reactor, serialport, baud)
+        self.is_shutdown = False
+        self._is_fileoutput = False
+        self._timeout_timer = printer.reactor.register_timer(
+            self.timeout_handler)
+        # Config building
+        self._emergency_stop_cmd = self._clear_shutdown_cmd = None
+        self._num_oids = 0
+        self._config_cmds = []
+        self._config_crc = None
+        self._init_callbacks = []
+        # Move command queuing
+        ffi_main, self.ffi_lib = chelper.get_ffi()
+        self._steppers = []
+        self._steppersync = None
+        # Print time to clock epoch calculations
+        self._print_start_time = 0.
+        self._mcu_freq = 0.
+        # Stats
+        self._mcu_tick_avg = 0.
+        self._mcu_tick_stddev = 0.
+    def handle_mcu_stats(self, params):
+        logging.debug("mcu stats: %s" % (params,))
+        count = params['count']
+        tick_sum = params['sum']
+        c = 1.0 / (count * self._mcu_freq)
+        self._mcu_tick_avg = tick_sum * c
+        tick_sumsq = params['sumsq']
+        tick_sumavgsq = ((tick_sum // (256*count)) * count)**2
+        self._mcu_tick_stddev = c * 256. * math.sqrt(
+            count * tick_sumsq - tick_sumavgsq)
+    def handle_shutdown(self, params):
+        if self.is_shutdown:
+            return
+        self.is_shutdown = True
+        logging.info("%s: %s" % (params['#name'], params['#msg']))
+        self.serial.dump_debug()
+        self._printer.note_shutdown(params['#msg'])
+    # Connection phase
+    def connect(self):
+        if not self._is_fileoutput:
+            self.serial.connect()
+            self._printer.reactor.update_timer(
+                self._timeout_timer, time.time() + self.COMM_TIMEOUT)
+        self._mcu_freq = float(self.serial.msgparser.config['CLOCK_FREQ'])
+        self._emergency_stop_cmd = self.lookup_command("emergency_stop")
+        self._clear_shutdown_cmd = self.lookup_command("clear_shutdown")
+        self.register_msg(self.handle_shutdown, 'shutdown')
+        self.register_msg(self.handle_shutdown, 'is_shutdown')
+        self.register_msg(self.handle_mcu_stats, 'stats')
+    def connect_file(self, debugoutput, dictionary, pace=False):
+        self._is_fileoutput = True
+        self.serial.connect_file(debugoutput, dictionary)
+        if not pace:
+            def dummy_set_print_start_time(eventtime):
+                pass
+            def dummy_get_print_buffer_time(eventtime, last_move_end):
+                return 0.250
+            self.set_print_start_time = dummy_set_print_start_time
+            self.get_print_buffer_time = dummy_get_print_buffer_time
+    def timeout_handler(self, eventtime):
+        last_clock, last_clock_time = self.serial.get_last_clock()
+        timeout = last_clock_time + self.COMM_TIMEOUT
+        if eventtime < timeout:
+            return timeout
+        logging.info("Timeout with firmware (eventtime=%f last_status=%f)" % (
+            eventtime, last_clock_time))
+        self._printer.note_mcu_error("Lost communication with firmware")
+        return self._printer.reactor.NEVER
+    def disconnect(self):
+        self.serial.disconnect()
+        if self._steppersync is not None:
+            self.ffi_lib.steppersync_free(self._steppersync)
+            self._steppersync = None
+    def stats(self, eventtime):
+        stats = self.serial.stats(eventtime)
+        stats += " mcu_task_avg=%.06f mcu_task_stddev=%.06f" % (
+            self._mcu_tick_avg, self._mcu_tick_stddev)
+        err = 0
+        for s in self._steppers:
+            err += s.get_errors()
+        if err:
+            stats += " step_errors=%d" % (err,)
+        return stats
+    def force_shutdown(self):
+        self.send(self._emergency_stop_cmd.encode())
+    def clear_shutdown(self):
+        logging.info("Sending clear_shutdown command")
+        self.send(self._clear_shutdown_cmd.encode())
+    def is_fileoutput(self):
+        return self._is_fileoutput
+    # Configuration phase
+    def _add_custom(self):
+        data = self._config.get('custom', '')
+        for line in data.split('\n'):
+            line = line.strip()
+            cpos = line.find('#')
+            if cpos >= 0:
+                line = line[:cpos].strip()
+            if not line:
+                continue
+            self.add_config_cmd(line)
+    def build_config(self):
+        # Build config commands
+        self._add_custom()
+        self._config_cmds.insert(0, "allocate_oids count=%d" % (
+            self._num_oids,))
+
+        # Resolve pin names
+        mcu = self.serial.msgparser.config['MCU']
+        pin_map = self._config.get('pin_map', None)
+        if pin_map is None:
+            pnames = pins.mcu_to_pins(mcu)
+        else:
+            pnames = pins.map_pins(pin_map, mcu)
+        updated_cmds = []
+        for cmd in self._config_cmds:
+            try:
+                updated_cmds.append(pins.update_command(cmd, pnames))
+            except:
+                raise self._config.error("Unable to translate pin name: %s" % (
+                    cmd,))
+        self._config_cmds = updated_cmds
+
+        # Calculate config CRC
+        self._config_crc = zlib.crc32('\n'.join(self._config_cmds)) & 0xffffffff
+        self.add_config_cmd("finalize_config crc=%d" % (self._config_crc,))
+
+        self._send_config()
+    def _send_config(self):
+        msg = self.create_command("get_config")
+        if self._is_fileoutput:
+            config_params = {
+                'is_config': 0, 'move_count': 500, 'crc': self._config_crc}
+        else:
+            config_params = self.serial.send_with_response(msg, 'config')
+        if not config_params['is_config']:
+            # Send config commands
+            for c in self._config_cmds:
+                self.send(self.create_command(c))
+            if not self._is_fileoutput:
+                config_params = self.serial.send_with_response(msg, 'config')
+        if self._config_crc != config_params['crc']:
+            raise error("Printer CRC does not match config")
+        logging.info("Configured")
+        stepqueues = tuple(s._stepqueue for s in self._steppers)
+        self._steppersync = self.ffi_lib.steppersync_alloc(
+            self.serial.serialqueue, stepqueues, len(stepqueues),
+            config_params['move_count'])
+        for cb in self._init_callbacks:
+            cb()
+    # Config creation helpers
+    def create_oid(self):
+        oid = self._num_oids
+        self._num_oids += 1
+        return oid
+    def add_config_cmd(self, cmd):
+        self._config_cmds.append(cmd)
+    def add_init_callback(self, callback):
+        self._init_callbacks.append(callback)
+    def register_msg(self, cb, msg, oid=None):
+        self.serial.register_callback(cb, msg, oid)
+    def register_stepper(self, stepper):
+        self._steppers.append(stepper)
+    def alloc_command_queue(self):
+        return self.serial.alloc_command_queue()
+    def lookup_command(self, msgformat):
+        return self.serial.msgparser.lookup_command(msgformat)
+    def create_command(self, msg):
+        return self.serial.msgparser.create_command(msg)
+    # Wrappers for mcu object creation
+    def create_stepper(self, step_pin, dir_pin, min_stop_interval, max_error):
+        return MCU_stepper(self, step_pin, dir_pin, min_stop_interval, max_error)
+    def create_endstop(self, pin, stepper):
+        return MCU_endstop(self, pin, stepper)
+    def create_digital_out(self, pin, max_duration=2.):
+        max_duration = int(max_duration * self._mcu_freq)
+        return MCU_digital_out(self, pin, max_duration)
+    def create_pwm(self, pin, hard_cycle_ticks, max_duration=2.):
+        max_duration = int(max_duration * self._mcu_freq)
+        if hard_cycle_ticks:
+            return MCU_pwm(self, pin, hard_cycle_ticks, max_duration)
+        if hard_cycle_ticks < 0:
+            return MCU_digital_out(self, pin, max_duration)
+        cycle_ticks = int(self._mcu_freq / 10.)
+        return MCU_pwm(self, pin, cycle_ticks, max_duration, hard_pwm=False)
+    def create_adc(self, pin):
+        return MCU_adc(self, pin)
+    # Clock syncing
+    def set_print_start_time(self, eventtime):
+        est_mcu_time = self.serial.get_clock(eventtime) / self._mcu_freq
+        self._print_start_time = est_mcu_time
+    def get_print_buffer_time(self, eventtime, print_time):
+        if self.is_shutdown:
+            return 0.
+        mcu_time = print_time + self._print_start_time
+        est_mcu_time = self.serial.get_clock(eventtime) / self._mcu_freq
+        return mcu_time - est_mcu_time
+    def print_to_mcu_time(self, print_time):
+        return print_time + self._print_start_time
+    def get_mcu_freq(self):
+        return self._mcu_freq
+    def get_last_clock(self):
+        return self.serial.get_last_clock()
+    # Move command queuing
+    def send(self, cmd, minclock=0, reqclock=0, cq=None):
+        self.serial.send(cmd, minclock, reqclock, cq=cq)
+    def flush_moves(self, print_time):
+        mcu_time = print_time + self._print_start_time
+        clock = int(mcu_time * self._mcu_freq)
+        self.ffi_lib.steppersync_flush(self._steppersync, clock)
+    def pause(self, waketime):
+        return self._printer.reactor.pause(waketime)
+    def __del__(self):
+        self.disconnect()

klippy/msgproto.py

@@ -0,0 +1,310 @@
+# Protocol definitions for firmware communication
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import json, zlib, logging
+
+DefaultMessages = {
+    0: "identify_response offset=%u data=%.*s",
+    1: "identify offset=%u count=%c",
+}
+
+MESSAGE_MIN = 5
+MESSAGE_MAX = 64
+MESSAGE_HEADER_SIZE  = 2
+MESSAGE_TRAILER_SIZE = 3
+MESSAGE_POS_LEN = 0
+MESSAGE_POS_SEQ = 1
+MESSAGE_TRAILER_CRC  = 3
+MESSAGE_TRAILER_SYNC = 1
+MESSAGE_PAYLOAD_MAX = MESSAGE_MAX - MESSAGE_MIN
+MESSAGE_SEQ_MASK = 0x0f
+MESSAGE_DEST = 0x10
+MESSAGE_SYNC = '\x7E'
+
+class error(Exception):
+    pass
+
+def crc16_ccitt(buf):
+    crc = 0xffff
+    for data in buf:
+        data = ord(data)
+        data ^= crc & 0xff
+        data ^= (data & 0x0f) << 4
+        crc = ((data << 8) | (crc >> 8)) ^ (data >> 4) ^ (data << 3)
+    crc = chr(crc >> 8) + chr(crc & 0xff)
+    return crc
+
+class PT_uint32:
+    is_int = 1
+    max_length = 5
+    signed = 0
+    def encode(self, out, v):
+        if v >= 0xc000000 or v < -0x4000000: out.append((v>>28) & 0x7f | 0x80)
+        if v >= 0x180000 or v < -0x80000:    out.append((v>>21) & 0x7f | 0x80)
+        if v >= 0x3000 or v < -0x1000:       out.append((v>>14) & 0x7f | 0x80)
+        if v >= 0x60 or v < -0x20:           out.append((v>>7)  & 0x7f | 0x80)
+        out.append(v & 0x7f)
+    def parse(self, s, pos):
+        c = s[pos]
+        pos += 1
+        v = c & 0x7f
+        if (c & 0x60) == 0x60:
+            v |= -0x20
+        while c & 0x80:
+            c = s[pos]
+            pos += 1
+            v = (v<<7) | (c & 0x7f)
+        if not self.signed:
+            v = int(v & 0xffffffff)
+        return v, pos
+
+class PT_int32(PT_uint32):
+    signed = 1
+class PT_uint16(PT_uint32):
+    max_length = 3
+class PT_int16(PT_int32):
+    signed = 1
+    max_length = 3
+class PT_byte(PT_uint32):
+    max_length = 2
+
+class PT_string:
+    is_int = 0
+    max_length = 64
+    def encode(self, out, v):
+        out.append(len(v))
+        out.extend(bytearray(v))
+    def parse(self, s, pos):
+        l = s[pos]
+        return str(bytearray(s[pos+1:pos+l+1])), pos+l+1
+class PT_progmem_buffer(PT_string):
+    pass
+class PT_buffer(PT_string):
+    pass
+
+MessageTypes = {
+    '%u': PT_uint32(), '%i': PT_int32(),
+    '%hu': PT_uint16(), '%hi': PT_int16(),
+    '%c': PT_byte(),
+    '%s': PT_string(), '%.*s': PT_progmem_buffer(), '%*s': PT_buffer(),
+}
+
+# Update the message format to be compatible with python's % operator
+def convert_msg_format(msgformat):
+    mf = msgformat.replace('%c', '%u')
+    mf = mf.replace('%.*s', '%s').replace('%*s', '%s')
+    return mf
+
+class MessageFormat:
+    def __init__(self, msgid, msgformat):
+        self.msgid = msgid
+        self.msgformat = msgformat
+        self.debugformat = convert_msg_format(msgformat)
+        parts = msgformat.split()
+        self.name = parts[0]
+        argparts = [arg.split('=') for arg in parts[1:]]
+        self.param_types = [MessageTypes[fmt] for name, fmt in argparts]
+        self.param_names = [name for name, fmt in argparts]
+        self.name_to_type = dict(zip(self.param_names, self.param_types))
+    def encode(self, *params):
+        out = []
+        out.append(self.msgid)
+        for i, t in enumerate(self.param_types):
+            t.encode(out, params[i])
+        return out
+    def encode_by_name(self, **params):
+        out = []
+        out.append(self.msgid)
+        for name, t in zip(self.param_names, self.param_types):
+            t.encode(out, params[name])
+        return out
+    def parse(self, s, pos):
+        pos += 1
+        out = {}
+        for t, name in zip(self.param_types, self.param_names):
+            v, pos = t.parse(s, pos)
+            out[name] = v
+        return out, pos
+    def dump(self, s, pos):
+        pos += 1
+        out = []
+        for t in self.param_types:
+            v, pos = t.parse(s, pos)
+            if not t.is_int:
+                v = repr(v)
+            out.append(v)
+        outmsg = self.debugformat % tuple(out)
+        return outmsg, pos
+
+class OutputFormat:
+    name = '#output'
+    def __init__(self, msgid, msgformat):
+        self.msgid = msgid
+        self.msgformat = msgformat
+        self.debugformat = convert_msg_format(msgformat)
+        self.param_types = []
+        args = msgformat
+        while 1:
+            pos = args.find('%')
+            if pos < 0:
+                break
+            if pos+1 >= len(args) or args[pos+1] != '%':
+                for i in range(4):
+                    t = MessageTypes.get(args[pos:pos+1+i])
+                    if t is not None:
+                        self.param_types.append(t)
+                        break
+                else:
+                    raise error("Invalid output format for '%s'" % (msg,))
+            args = args[pos+1:]
+    def parse(self, s, pos):
+        pos += 1
+        out = []
+        for t in self.param_types:
+            v, pos = t.parse(s, pos)
+            out.append(v)
+        outmsg = self.debugformat % tuple(out)
+        return {'#msg': outmsg}, pos
+    def dump(self, s, pos):
+        pos += 1
+        out = []
+        for t in self.param_types:
+            v, pos = t.parse(s, pos)
+            out.append(v)
+        outmsg = self.debugformat % tuple(out)
+        return outmsg, pos
+
+class UnknownFormat:
+    name = '#unknown'
+    def parse(self, s, pos):
+        msgid = s[pos]
+        msg = str(bytearray(s))
+        return {'#msgid': msgid, '#msg': msg}, len(s)-MESSAGE_TRAILER_SIZE
+
+class MessageParser:
+    def __init__(self):
+        self.unknown = UnknownFormat()
+        self.messages_by_id = {}
+        self.messages_by_name = {}
+        self.static_strings = []
+        self.config = {}
+        self.version = ""
+        self.raw_identify_data = ""
+        self._init_messages(DefaultMessages, DefaultMessages.keys())
+    def check_packet(self, s):
+        if len(s) < MESSAGE_MIN:
+            return 0
+        msglen = ord(s[MESSAGE_POS_LEN])
+        if msglen < MESSAGE_MIN or msglen > MESSAGE_MAX:
+            return -1
+        msgseq = ord(s[MESSAGE_POS_SEQ])
+        if (msgseq & ~MESSAGE_SEQ_MASK) != MESSAGE_DEST:
+            return -1
+        if len(s) < msglen:
+            # Need more data
+            return 0
+        if s[msglen-MESSAGE_TRAILER_SYNC] != MESSAGE_SYNC:
+            return -1
+        msgcrc = s[msglen-MESSAGE_TRAILER_CRC:msglen-MESSAGE_TRAILER_CRC+2]
+        crc = crc16_ccitt(s[:msglen-MESSAGE_TRAILER_SIZE])
+        if crc != msgcrc:
+            #logging.debug("got crc %s vs %s" % (repr(crc), repr(msgcrc)))
+            return -1
+        return msglen
+    def dump(self, s):
+        msgseq = s[MESSAGE_POS_SEQ]
+        out = ["seq: %02x" % (msgseq,)]
+        pos = MESSAGE_HEADER_SIZE
+        while 1:
+            msgid = s[pos]
+            mid = self.messages_by_id.get(msgid, self.unknown)
+            params, pos = mid.dump(s, pos)
+            out.append("%s" % (params,))
+            if pos >= len(s)-MESSAGE_TRAILER_SIZE:
+                break
+        return out
+    def parse(self, s):
+        msgid = s[MESSAGE_HEADER_SIZE]
+        mid = self.messages_by_id.get(msgid, self.unknown)
+        params, pos = mid.parse(s, MESSAGE_HEADER_SIZE)
+        if pos != len(s)-MESSAGE_TRAILER_SIZE:
+            raise error("Extra data at end of message")
+        params['#name'] = mid.name
+        static_string_id = params.get('static_string_id')
+        if static_string_id is not None:
+            params['#msg'] = self.static_strings[static_string_id]
+        return params
+    def encode(self, seq, cmd):
+        msglen = MESSAGE_MIN + len(cmd)
+        seq = (seq & MESSAGE_SEQ_MASK) | MESSAGE_DEST
+        out = [chr(msglen), chr(seq), cmd]
+        out.append(crc16_ccitt(''.join(out)))
+        out.append(MESSAGE_SYNC)
+        return ''.join(out)
+    def _parse_buffer(self, value):
+        tval = int(value, 16)
+        out = []
+        for i in range(len(value)/2):
+            out.append(tval & 0xff)
+            tval >>= 8
+        out.reverse()
+        return ''.join([chr(i) for i in out])
+    def lookup_command(self, msgformat):
+        parts = msgformat.strip().split()
+        msgname = parts[0]
+        mp = self.messages_by_name.get(msgname)
+        if mp is None:
+            raise error("Unknown command: %s" % (msgname,))
+        if msgformat != mp.msgformat:
+            raise error("Command format mismatch: %s vs %s" % (
+                msgformat, mp.msgformat))
+        return mp
+    def create_command(self, msg):
+        parts = msg.strip().split()
+        if not parts:
+            return ""
+        msgname = parts[0]
+        mp = self.messages_by_name.get(msgname)
+        if mp is None:
+            raise error("Unknown command: %s" % (msgname,))
+        try:
+            argparts = dict(arg.split('=', 1) for arg in parts[1:])
+            for name, value in argparts.items():
+                t = mp.name_to_type[name]
+                if t.is_int:
+                    tval = int(value, 0)
+                else:
+                    tval = self._parse_buffer(value)
+                argparts[name] = tval
+        except:
+            #traceback.print_exc()
+            raise error("Unable to extract params from: %s" % (msgname,))
+        try:
+            cmd = mp.encode_by_name(**argparts)
+        except:
+            #traceback.print_exc()
+            raise error("Unable to encode: %s" % (msgname,))
+        return cmd
+    def _init_messages(self, messages, parsers):
+        for msgid, msgformat in messages.items():
+            msgid = int(msgid)
+            if msgid not in parsers:
+                self.messages_by_id[msgid] = OutputFormat(msgid, msgformat)
+                continue
+            msg = MessageFormat(msgid, msgformat)
+            self.messages_by_id[msgid] = msg
+            self.messages_by_name[msg.name] = msg
+    def process_identify(self, data, decompress=True):
+        if decompress:
+            data = zlib.decompress(data)
+        self.raw_identify_data = data
+        data = json.loads(data)
+        messages = data.get('messages')
+        commands = data.get('commands')
+        responses = data.get('responses')
+        self._init_messages(messages, commands+responses)
+        self.static_strings = data.get('static_strings', [])
+        self.config.update(data.get('config', {}))
+        self.version = data.get('version', '')

klippy/parsedump.py

@@ -0,0 +1,45 @@
+#!/usr/bin/env python
+# Script to parse a serial port data dump
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import os, sys, logging
+import msgproto
+
+def read_dictionary(filename):
+    dfile = open(filename, 'rb')
+    dictionary = dfile.read()
+    dfile.close()
+    return dictionary
+
+def main():
+    dict_filename, data_filename = sys.argv[1:]
+
+    dictionary = read_dictionary(dict_filename)
+
+    mp = msgproto.MessageParser()
+    mp.process_identify(dictionary, decompress=False)
+
+    f = open(data_filename, 'rb')
+    fd = f.fileno()
+    data = ""
+    while 1:
+        newdata = os.read(fd, 4096)
+        if not newdata:
+            break
+        data += newdata
+        while 1:
+            l = mp.check_packet(data)
+            if l == 0:
+                break
+            if l < 0:
+                logging.error("Invalid data")
+                data = data[-l:]
+                continue
+            msgs = mp.dump(bytearray(data[:l]))
+            sys.stdout.write('\n'.join(msgs[1:]) + '\n')
+            data = data[l:]
+
+if __name__ == '__main__':
+    main()

klippy/pins.py

@@ -0,0 +1,107 @@
+# Pin name to pin number definitions
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+
+import re
+
+def port_pins(port_count, bit_count=8):
+    pins = {}
+    for port in range(port_count):
+        portchr = chr(65 + port)
+        if portchr == 'I':
+            continue
+        for portbit in range(bit_count):
+            pins['P%c%d' % (portchr, portbit)] = port * bit_count + portbit
+    return pins
+
+PINS_atmega164 = port_pins(4)
+PINS_atmega1280 = port_pins(12)
+
+MCU_PINS = {
+    "atmega168": PINS_atmega164, "atmega644p": PINS_atmega164,
+    "at90usb1286": port_pins(5),
+    "atmega1280": PINS_atmega1280, "atmega2560": PINS_atmega1280,
+    "sam3x8e": port_pins(4, 32)
+}
+
+def mcu_to_pins(mcu):
+    return MCU_PINS.get(mcu, {})
+
+re_pin = re.compile(r'(?P<prefix>[ _]pin=)(?P<name>[^ ]*)')
+def update_command(cmd, pmap):
+    def fixup(m):
+        return m.group('prefix') + str(pmap[m.group('name')])
+    return re_pin.sub(fixup, cmd)
+
+
+######################################################################
+# Arduino mappings
+######################################################################
+
+Arduino_standard = [
+    "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PB0", "PB1",
+    "PB2", "PB3", "PB4", "PB5", "PC0", "PC1", "PC2", "PC3", "PC4", "PC5",
+]
+Arduino_analog_standard = [
+    "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PE0", "PE1",
+]
+
+Arduino_mega = [
+    "PE0", "PE1", "PE4", "PE5", "PG5", "PE3", "PH3", "PH4", "PH5", "PH6",
+    "PB4", "PB5", "PB6", "PB7", "PJ1", "PJ0", "PH1", "PH0", "PD3", "PD2",
+    "PD1", "PD0", "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
+    "PC7", "PC6", "PC5", "PC4", "PC3", "PC2", "PC1", "PC0", "PD7", "PG2",
+    "PG1", "PG0", "PL7", "PL6", "PL5", "PL4", "PL3", "PL2", "PL1", "PL0",
+    "PB3", "PB2", "PB1", "PB0", "PF0", "PF1", "PF2", "PF3", "PF4", "PF5",
+    "PF6", "PF7", "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
+]
+Arduino_analog_mega = [
+    "PF0", "PF1", "PF2", "PF3", "PF4", "PF5",
+    "PF6", "PF7", "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
+]
+
+Sanguino = [
+    "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", "PD0", "PD1",
+    "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PC0", "PC1", "PC2", "PC3",
+    "PC4", "PC5", "PC6", "PC7", "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
+    "PA6", "PA7"
+]
+Sanguino_analog = [
+    "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7"
+]
+
+Arduino_Due = [
+    "PA8", "PA9", "PB25", "PC28", "PA29", "PC25", "PC24", "PC23", "PC22", "PC21",
+    "PA28", "PD7", "PD8", "PB27", "PD4", "PD5", "PA13", "PA12", "PA11", "PA10",
+    "PB12", "PB13", "PB26", "PA14", "PA15", "PD0", "PD1", "PD2", "PD3", "PD6",
+    "PD9", "PA7", "PD10", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",
+    "PC8", "PC9", "PA19", "PA20", "PC19", "PC18", "PC17", "PC16", "PC15", "PC14",
+    "PC13", "PC12", "PB21", "PB14", "PA16", "PA24", "PA23", "PA22", "PA6", "PA4",
+    "PA3", "PA2", "PB17", "PB18", "PB19", "PB20", "PB15", "PB16", "PA1", "PA0",
+    "PA17", "PA18", "PC30", "PA21", "PA25", "PA26", "PA27", "PA28", "PB23"
+]
+Arduino_Due_analog = [
+    "PA16", "PA24", "PA23", "PA22", "PA6", "PA4", "PA3", "PA2", "PB17", "PB18",
+    "PB19", "PB20"
+]
+
+
+Arduino_from_mcu = {
+    "atmega168": (Arduino_standard, Arduino_analog_standard),
+    "atmega644p": (Sanguino, Sanguino_analog),
+    "atmega1280": (Arduino_mega, Arduino_analog_mega),
+    "atmega2560": (Arduino_mega, Arduino_analog_mega),
+    "sam3x8e": (Arduino_Due, Arduino_Due_analog),
+}
+
+def map_pins(name, mcu):
+    pins = MCU_PINS.get(mcu, {})
+    if name == 'arduino':
+        dpins, apins = Arduino_from_mcu.get(mcu, [])
+        for i in range(len(dpins)):
+            pins['ar' + str(i)] = pins[dpins[i]]
+        for i in range(len(apins)):
+            pins['analog%d' % (i,)] = pins[apins[i]]
+    return pins

klippy/pyhelper.c

@@ -0,0 +1,90 @@
+// Helper functions for C / Python interface
+//
+// Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+//
+// This file may be distributed under the terms of the GNU GPLv3 license.
+
+#include <errno.h> // errno
+#include <stdarg.h> // va_start
+#include <stdint.h> // uint8_t
+#include <stdio.h> // fprintf
+#include <string.h> // strerror
+#include <sys/time.h> // gettimeofday
+#include <time.h> // struct timespec
+#include "pyhelper.h" // get_time
+
+// Return the current system time as a double
+double
+get_time(void)
+{
+    struct timeval tv;
+    gettimeofday(&tv, NULL);
+    return (double)tv.tv_sec + (double)tv.tv_usec / 1000000.;
+}
+
+// Fill a 'struct timespec' with a system time stored in a double
+struct timespec
+fill_time(double time)
+{
+    time_t t = time;
+    return (struct timespec) {t, (time - t)*1000000000. };
+}
+
+static void
+default_logger(const char *msg)
+{
+    fprintf(stderr, "%s\n", msg);
+}
+
+static void (*python_logging_callback)(const char *msg) = default_logger;
+
+void
+set_python_logging_callback(void (*func)(const char *))
+{
+    python_logging_callback = func;
+}
+
+// Log an error message
+void
+errorf(const char *fmt, ...)
+{
+    char buf[512];
+    va_list args;
+    va_start(args, fmt);
+    vsnprintf(buf, sizeof(buf), fmt, args);
+    va_end(args);
+    buf[sizeof(buf)-1] = '\0';
+    python_logging_callback(buf);
+}
+
+// Report 'errno' in a message written to stderr
+void
+report_errno(char *where, int rc)
+{
+    int e = errno;
+    errorf("Got error %d in %s: (%d)%s", rc, where, e, strerror(e));
+}
+
+// Return a hex character for a given number
+#define GETHEX(x) ((x) < 10 ? '0' + (x) : 'e' + (x) - 10)
+
+// Translate a binary string into an ASCII string with escape sequences
+char *
+dump_string(char *outbuf, int outbuf_size, char *inbuf, int inbuf_size)
+{
+    char *outend = &outbuf[outbuf_size-5], *o = outbuf;
+    uint8_t *inend = (void*)&inbuf[inbuf_size], *p = (void*)inbuf;
+    while (p < inend && o < outend) {
+        uint8_t c = *p++;
+        if (c > 31 && c < 127 && c != '\\') {
+            *o++ = c;
+            continue;
+        }
+        *o++ = '\\';
+        *o++ = 'x';
+        *o++ = GETHEX(c >> 4);
+        *o++ = GETHEX(c & 0x0f);
+    }
+    *o = '\0';
+    return outbuf;
+}

klippy/pyhelper.h

@@ -0,0 +1,11 @@
+#ifndef PYHELPER_H
+#define PYHELPER_H
+
+double get_time(void);
+struct timespec fill_time(double time);
+void set_python_logging_callback(void (*func)(const char *));
+void errorf(const char *fmt, ...) __attribute__ ((format (printf, 1, 2)));
+void report_errno(char *where, int rc);
+char *dump_string(char *outbuf, int outbuf_size, char *inbuf, int inbuf_size);
+
+#endif // pyhelper.h

klippy/queuelogger.py

@@ -0,0 +1,48 @@
+# Code to implement asynchronous logging from a background thread
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import logging, threading, Queue
+
+# Class to forward all messages through a queue to a background thread
+class QueueHandler(logging.Handler):
+    def __init__(self, queue):
+        logging.Handler.__init__(self)
+        self.queue = queue
+    def emit(self, record):
+        try:
+            self.format(record)
+            record.msg = record.message
+            record.args = None
+            record.exc_info = None
+            self.queue.put_nowait(record)
+        except Exception:
+            self.handleError(record)
+
+# Class to poll a queue in a background thread and log each message
+class QueueListener(object):
+    def __init__(self, handler):
+        self.handler = handler
+        self.queue = Queue.Queue()
+        self.thread = threading.Thread(target=self._bg_thread)
+        self.thread.start()
+    def _bg_thread(self):
+        while 1:
+            record = self.queue.get(True)
+            if record is None:
+                break
+            self.handler.handle(record)
+    def stop(self):
+        self.queue.put_nowait(None)
+        self.thread.join()
+
+def setup_bg_logging(filename, debuglevel):
+    logoutput = open(filename, 'wb')
+    handler = logging.StreamHandler(logoutput)
+    ql = QueueListener(handler)
+    qh = QueueHandler(ql.queue)
+    root = logging.getLogger()
+    root.addHandler(qh)
+    root.setLevel(debuglevel)
+    return ql

klippy/reactor.py

@@ -0,0 +1,190 @@
+# File descriptor and timer event helper
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import select, time, math
+import greenlet
+
+class ReactorTimer:
+    def __init__(self, callback, waketime):
+        self.callback = callback
+        self.waketime = waketime
+
+class ReactorFileHandler:
+    def __init__(self, fd, callback):
+        self.fd = fd
+        self.callback = callback
+    def fileno(self):
+        return self.fd
+
+class ReactorGreenlet(greenlet.greenlet):
+    def __init__(self, run):
+        greenlet.greenlet.__init__(self, run=run)
+        self.timer = None
+
+class SelectReactor:
+    NOW = 0.
+    NEVER = 9999999999999999.
+    def __init__(self):
+        self._fds = []
+        self._timers = []
+        self._next_timer = self.NEVER
+        self._process = False
+        self._g_dispatch = None
+        self._greenlets = []
+    # Timers
+    def _note_time(self, t):
+        nexttime = t.waketime
+        if nexttime < self._next_timer:
+            self._next_timer = nexttime
+    def update_timer(self, t, nexttime):
+        t.waketime = nexttime
+        self._note_time(t)
+    def register_timer(self, callback, waketime = NEVER):
+        handler = ReactorTimer(callback, waketime)
+        timers = list(self._timers)
+        timers.append(handler)
+        self._timers = timers
+        self._note_time(handler)
+        return handler
+    def unregister_timer(self, handler):
+        timers = list(self._timers)
+        timers.pop(timers.index(handler))
+        self._timers = timers
+    def _check_timers(self, eventtime):
+        if eventtime < self._next_timer:
+            return min(1., max(.001, self._next_timer - eventtime))
+        self._next_timer = self.NEVER
+        g_dispatch = self._g_dispatch
+        for t in self._timers:
+            if eventtime >= t.waketime:
+                t.waketime = self.NEVER
+                t.waketime = t.callback(eventtime)
+                if g_dispatch is not self._g_dispatch:
+                    self._end_greenlet(g_dispatch)
+                    return 0.
+            self._note_time(t)
+        if eventtime >= self._next_timer:
+            return 0.
+        return min(1., max(.001, self._next_timer - time.time()))
+    # Greenlets
+    def pause(self, waketime):
+        g = greenlet.getcurrent()
+        if g is not self._g_dispatch:
+            return self._g_dispatch.switch(waketime)
+        if self._greenlets:
+            g_next = self._greenlets.pop()
+        else:
+            g_next = ReactorGreenlet(run=self._dispatch_loop)
+        g_next.parent = g.parent
+        g.timer = self.register_timer(g.switch, waketime)
+        return g_next.switch()
+    def _end_greenlet(self, g_old):
+        self._greenlets.append(g_old)
+        self.unregister_timer(g_old.timer)
+        g_old.timer = None
+        self._g_dispatch.switch(self.NEVER)
+        self._g_dispatch = g_old
+    # File descriptors
+    def register_fd(self, fd, callback):
+        handler = ReactorFileHandler(fd, callback)
+        self._fds.append(handler)
+        return handler
+    def unregister_fd(self, handler):
+        self._fds.pop(self._fds.index(handler))
+    # Main loop
+    def _dispatch_loop(self):
+        self._process = True
+        self._g_dispatch = g_dispatch = greenlet.getcurrent()
+        eventtime = time.time()
+        while self._process:
+            timeout = self._check_timers(eventtime)
+            res = select.select(self._fds, [], [], timeout)
+            eventtime = time.time()
+            for fd in res[0]:
+                fd.callback(eventtime)
+                if g_dispatch is not self._g_dispatch:
+                    self._end_greenlet(g_dispatch)
+                    break
+        self._g_dispatch = None
+    def run(self):
+        g_next = ReactorGreenlet(run=self._dispatch_loop)
+        g_next.switch()
+    def end(self):
+        self._process = False
+
+class PollReactor(SelectReactor):
+    def __init__(self):
+        SelectReactor.__init__(self)
+        self._poll = select.poll()
+        self._fds = {}
+    # File descriptors
+    def register_fd(self, fd, callback):
+        handler = ReactorFileHandler(fd, callback)
+        fds = self._fds.copy()
+        fds[fd] = callback
+        self._fds = fds
+        self._poll.register(handler, select.POLLIN | select.POLLHUP)
+        return handler
+    def unregister_fd(self, handler):
+        self._poll.unregister(handler)
+        fds = self._fds.copy()
+        del fds[handler.fd]
+        self._fds = fds
+    # Main loop
+    def _dispatch_loop(self):
+        self._process = True
+        self._g_dispatch = g_dispatch = greenlet.getcurrent()
+        eventtime = time.time()
+        while self._process:
+            timeout = int(math.ceil(self._check_timers(eventtime) * 1000.))
+            res = self._poll.poll(timeout)
+            eventtime = time.time()
+            for fd, event in res:
+                self._fds[fd](eventtime)
+                if g_dispatch is not self._g_dispatch:
+                    self._end_greenlet(g_dispatch)
+                    break
+        self._g_dispatch = None
+
+class EPollReactor(SelectReactor):
+    def __init__(self):
+        SelectReactor.__init__(self)
+        self._epoll = select.epoll()
+        self._fds = {}
+    # File descriptors
+    def register_fd(self, fd, callback):
+        handler = ReactorFileHandler(fd, callback)
+        fds = self._fds.copy()
+        fds[fd] = callback
+        self._fds = fds
+        self._epoll.register(fd, select.EPOLLIN | select.EPOLLHUP)
+        return handler
+    def unregister_fd(self, handler):
+        self._epoll.unregister(handler.fd)
+        fds = self._fds.copy()
+        del fds[handler.fd]
+        self._fds = fds
+    # Main loop
+    def _dispatch_loop(self):
+        self._process = True
+        self._g_dispatch = g_dispatch = greenlet.getcurrent()
+        eventtime = time.time()
+        while self._process:
+            timeout = self._check_timers(eventtime)
+            res = self._epoll.poll(timeout)
+            eventtime = time.time()
+            for fd, event in res:
+                self._fds[fd](eventtime)
+                if g_dispatch is not self._g_dispatch:
+                    self._end_greenlet(g_dispatch)
+                    break
+        self._g_dispatch = None
+
+# Use the poll based reactor if it is available
+try:
+    select.poll
+    Reactor = PollReactor
+except:
+    Reactor = SelectReactor

klippy/serialhdl.py

@@ -0,0 +1,314 @@
+# Serial port management for firmware communication
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import time, logging, threading
+import serial
+
+import msgproto, chelper, util
+
+class SerialReader:
+    BITS_PER_BYTE = 10.
+    def __init__(self, reactor, serialport, baud):
+        self.reactor = reactor
+        self.serialport = serialport
+        self.baud = baud
+        # Serial port
+        self.ser = None
+        self.msgparser = msgproto.MessageParser()
+        # C interface
+        self.ffi_main, self.ffi_lib = chelper.get_ffi()
+        self.serialqueue = None
+        self.default_cmd_queue = self.alloc_command_queue()
+        self.stats_buf = self.ffi_main.new('char[4096]')
+        # MCU time/clock tracking
+        self.last_ack_time = self.last_ack_rtt_time = 0.
+        self.last_ack_clock = self.last_ack_rtt_clock = 0
+        self.est_clock = 0.
+        # Threading
+        self.lock = threading.Lock()
+        self.background_thread = None
+        # Message handlers
+        self.status_timer = self.reactor.register_timer(
+            self._status_event, self.reactor.NOW)
+        self.status_cmd = None
+        handlers = {
+            '#unknown': self.handle_unknown,
+            '#output': self.handle_output, 'status': self.handle_status,
+            'shutdown': self.handle_output, 'is_shutdown': self.handle_output
+        }
+        self.handlers = dict(((k, None), v) for k, v in handlers.items())
+    def _bg_thread(self):
+        response = self.ffi_main.new('struct pull_queue_message *')
+        while 1:
+            self.ffi_lib.serialqueue_pull(self.serialqueue, response)
+            count = response.len
+            if count <= 0:
+                break
+            params = self.msgparser.parse(response.msg[0:count])
+            params['#sent_time'] = response.sent_time
+            params['#receive_time'] = response.receive_time
+            with self.lock:
+                hdl = (params['#name'], params.get('oid'))
+                hdl = self.handlers.get(hdl, self.handle_default)
+            try:
+                hdl(params)
+            except:
+                logging.exception("Exception in serial callback")
+    def connect(self):
+        # Initial connection
+        logging.info("Starting serial connect")
+        while 1:
+            starttime = time.time()
+            try:
+                self.ser = serial.Serial(self.serialport, self.baud, timeout=0)
+            except OSError, e:
+                logging.warn("Unable to open port: %s" % (e,))
+                self.reactor.pause(starttime + 5.)
+                continue
+            stk500v2_leave(self.ser, self.reactor)
+            self.serialqueue = self.ffi_lib.serialqueue_alloc(
+                self.ser.fileno(), 0)
+            self.background_thread = threading.Thread(target=self._bg_thread)
+            self.background_thread.start()
+            # Obtain and load the data dictionary from the firmware
+            sbs = SerialBootStrap(self)
+            identify_data = sbs.get_identify_data(starttime + 5.)
+            if identify_data is None:
+                logging.warn("Timeout on serial connect")
+                self.disconnect()
+                self.ser.close()
+                self.ser = None
+                continue
+            break
+        msgparser = msgproto.MessageParser()
+        msgparser.process_identify(identify_data)
+        self.msgparser = msgparser
+        self.register_callback(self.handle_unknown, '#unknown')
+        logging.info("Loaded %d commands (%s)" % (
+            len(msgparser.messages_by_id), msgparser.version))
+        # Setup for runtime
+        mcu_baud = float(msgparser.config.get('SERIAL_BAUD', 0.))
+        if mcu_baud:
+            baud_adjust = self.BITS_PER_BYTE / mcu_baud
+            self.ffi_lib.serialqueue_set_baud_adjust(
+                self.serialqueue, baud_adjust)
+        get_status = msgparser.lookup_command('get_status')
+        self.status_cmd = get_status.encode()
+    def connect_file(self, debugoutput, dictionary, pace=False):
+        self.ser = debugoutput
+        self.msgparser.process_identify(dictionary, decompress=False)
+        est_clock = 1000000000000.
+        if pace:
+            est_clock = float(self.msgparser.config['CLOCK_FREQ'])
+        self.serialqueue = self.ffi_lib.serialqueue_alloc(self.ser.fileno(), 1)
+        self.est_clock = est_clock
+        self.last_ack_time = time.time()
+        self.last_ack_clock = 0
+        self.ffi_lib.serialqueue_set_clock_est(
+            self.serialqueue, self.est_clock, self.last_ack_time
+            , self.last_ack_clock)
+    def disconnect(self):
+        if self.serialqueue is None:
+            return
+        self.ffi_lib.serialqueue_exit(self.serialqueue)
+        if self.background_thread is not None:
+            self.background_thread.join()
+        self.ffi_lib.serialqueue_free(self.serialqueue)
+        self.background_thread = self.serialqueue = None
+    def stats(self, eventtime):
+        if self.serialqueue is None:
+            return ""
+        sqstats = self.ffi_lib.serialqueue_get_stats(
+            self.serialqueue, self.stats_buf, len(self.stats_buf))
+        sqstats = self.ffi_main.string(self.stats_buf)
+        tstats = " est_clock=%.3f last_ack_time=%.3f last_ack_clock=%d" % (
+            self.est_clock, self.last_ack_time, self.last_ack_clock)
+        return sqstats + tstats
+    def _status_event(self, eventtime):
+        if self.status_cmd is None:
+            return eventtime + 0.1
+        self.send(self.status_cmd)
+        return eventtime + 1.0
+    # Serial response callbacks
+    def register_callback(self, callback, name, oid=None):
+        with self.lock:
+            self.handlers[name, oid] = callback
+    def unregister_callback(self, name, oid=None):
+        with self.lock:
+            del self.handlers[name, oid]
+    # Clock tracking
+    def get_clock(self, eventtime):
+        with self.lock:
+            return int(self.last_ack_clock
+                       + (eventtime - self.last_ack_time) * self.est_clock)
+    def translate_clock(self, raw_clock):
+        with self.lock:
+            last_ack_clock = self.last_ack_clock
+        clock_diff = (last_ack_clock - raw_clock) & 0xffffffff
+        if clock_diff & 0x80000000:
+            return last_ack_clock + 0x100000000 - clock_diff
+        return last_ack_clock - clock_diff
+    def get_last_clock(self):
+        with self.lock:
+            return self.last_ack_clock, self.last_ack_time
+    # Command sending
+    def send(self, cmd, minclock=0, reqclock=0, cq=None):
+        if cq is None:
+            cq = self.default_cmd_queue
+        self.ffi_lib.serialqueue_send(
+            self.serialqueue, cq, cmd, len(cmd), minclock, reqclock)
+    def encode_and_send(self, data, minclock, reqclock, cq):
+        self.ffi_lib.serialqueue_encode_and_send(
+            self.serialqueue, cq, data, len(data), minclock, reqclock)
+    def send_with_response(self, cmd, name):
+        src = SerialRetryCommand(self, cmd, name)
+        return src.get_response()
+    def send_flush(self):
+        self.ffi_lib.serialqueue_flush_ready(self.serialqueue)
+    def alloc_command_queue(self):
+        return self.ffi_main.gc(self.ffi_lib.serialqueue_alloc_commandqueue(),
+                                self.ffi_lib.serialqueue_free_commandqueue)
+    # Dumping debug lists
+    def dump_debug(self):
+        sdata = self.ffi_main.new('struct pull_queue_message[1024]')
+        rdata = self.ffi_main.new('struct pull_queue_message[1024]')
+        scount = self.ffi_lib.serialqueue_extract_old(
+            self.serialqueue, 1, sdata, len(sdata))
+        rcount = self.ffi_lib.serialqueue_extract_old(
+            self.serialqueue, 0, rdata, len(rdata))
+        logging.info("Dumping send queue %d messages" % (scount,))
+        for i in range(scount):
+            msg = sdata[i]
+            cmds = self.msgparser.dump(msg.msg[0:msg.len])
+            logging.info("Sent %d %f %f %d: %s" % (
+                i, msg.receive_time, msg.sent_time, msg.len, ', '.join(cmds)))
+        logging.info("Dumping receive queue %d messages" % (rcount,))
+        for i in range(rcount):
+            msg = rdata[i]
+            cmds = self.msgparser.dump(msg.msg[0:msg.len])
+            logging.info("Receive: %d %f %f %d: %s" % (
+                i, msg.receive_time, msg.sent_time, msg.len, ', '.join(cmds)))
+    # Default message handlers
+    def handle_status(self, params):
+        with self.lock:
+            # Update last_ack_time / last_ack_clock
+            ack_clock = (self.last_ack_clock & ~0xffffffff) | params['clock']
+            if ack_clock < self.last_ack_clock:
+                ack_clock += 0x100000000
+            sent_time = params['#sent_time']
+            self.last_ack_time = receive_time = params['#receive_time']
+            self.last_ack_clock = ack_clock
+            # Update est_clock (if applicable)
+            if receive_time > self.last_ack_rtt_time + 1. and sent_time:
+                if self.last_ack_rtt_time:
+                    timedelta = receive_time - self.last_ack_rtt_time
+                    clockdelta = ack_clock - self.last_ack_rtt_clock
+                    estclock = clockdelta / timedelta
+                    if estclock > self.est_clock and self.est_clock:
+                        self.est_clock = (self.est_clock * 63. + estclock) / 64.
+                    else:
+                        self.est_clock = estclock
+                self.last_ack_rtt_time = sent_time
+                self.last_ack_rtt_clock = ack_clock
+            self.ffi_lib.serialqueue_set_clock_est(
+                self.serialqueue, self.est_clock, receive_time, ack_clock)
+    def handle_unknown(self, params):
+        logging.warn("Unknown message type %d: %s" % (
+            params['#msgid'], repr(params['#msg'])))
+    def handle_output(self, params):
+        logging.info("%s: %s" % (params['#name'], params['#msg']))
+    def handle_default(self, params):
+        logging.warn("got %s" % (params,))
+    def __del__(self):
+        self.disconnect()
+
+# Class to retry sending of a query command until a given response is received
+class SerialRetryCommand:
+    RETRY_TIME = 0.500
+    def __init__(self, serial, cmd, name):
+        self.serial = serial
+        self.cmd = cmd
+        self.name = name
+        self.response = None
+        self.min_query_time = time.time()
+        self.serial.register_callback(self.handle_callback, self.name)
+        self.send_timer = self.serial.reactor.register_timer(
+            self.send_event, self.serial.reactor.NOW)
+    def send_event(self, eventtime):
+        if self.response is not None:
+            return self.serial.reactor.NEVER
+        self.serial.send(self.cmd)
+        return eventtime + self.RETRY_TIME
+    def handle_callback(self, params):
+        last_sent_time = params['#sent_time']
+        if last_sent_time >= self.min_query_time:
+            self.response = params
+    def get_response(self):
+        eventtime = time.time()
+        while self.response is None:
+            eventtime = self.serial.reactor.pause(eventtime + 0.05)
+        self.serial.unregister_callback(self.name)
+        self.serial.reactor.unregister_timer(self.send_timer)
+        return self.response
+
+# Code to start communication and download message type dictionary
+class SerialBootStrap:
+    RETRY_TIME = 0.500
+    def __init__(self, serial):
+        self.serial = serial
+        self.identify_data = ""
+        self.identify_cmd = self.serial.msgparser.lookup_command(
+            "identify offset=%u count=%c")
+        self.is_done = False
+        self.serial.register_callback(self.handle_identify, 'identify_response')
+        self.serial.register_callback(self.handle_unknown, '#unknown')
+        self.send_timer = self.serial.reactor.register_timer(
+            self.send_event, self.serial.reactor.NOW)
+    def get_identify_data(self, timeout):
+        eventtime = time.time()
+        while not self.is_done and eventtime <= timeout:
+            eventtime = self.serial.reactor.pause(eventtime + 0.05)
+        self.serial.unregister_callback('identify_response')
+        self.serial.reactor.unregister_timer(self.send_timer)
+        if not self.is_done:
+            return None
+        return self.identify_data
+    def handle_identify(self, params):
+        if self.is_done or params['offset'] != len(self.identify_data):
+            return
+        msgdata = params['data']
+        if not msgdata:
+            self.is_done = True
+            return
+        self.identify_data += msgdata
+        imsg = self.identify_cmd.encode(len(self.identify_data), 40)
+        self.serial.send(imsg)
+    def send_event(self, eventtime):
+        if self.is_done:
+            return self.serial.reactor.NEVER
+        imsg = self.identify_cmd.encode(len(self.identify_data), 40)
+        self.serial.send(imsg)
+        return eventtime + self.RETRY_TIME
+    def handle_unknown(self, params):
+        logging.debug("Unknown message %d (len %d) while identifying" % (
+            params['#msgid'], len(params['#msg'])))
+
+# Attempt to place an AVR stk500v2 style programmer into normal mode
+def stk500v2_leave(ser, reactor):
+    logging.debug("Starting stk500v2 leave programmer sequence")
+    util.clear_hupcl(ser.fileno())
+    origbaud = ser.baudrate
+    # Request a dummy speed first as this seems to help reset the port
+    ser.baudrate = 2400
+    ser.read(1)
+    # Send stk500v2 leave programmer sequence
+    ser.baudrate = 115200
+    reactor.pause(time.time() + 0.100)
+    ser.read(4096)
+    ser.write('\x1b\x01\x00\x01\x0e\x11\x04')
+    reactor.pause(time.time() + 0.050)
+    res = ser.read(4096)
+    logging.debug("Got %s from stk500v2" % (repr(res),))
+    ser.baudrate = origbaud

klippy/serialqueue.h

@@ -0,0 +1,69 @@
+#ifndef SERIALQUEUE_H
+#define SERIALQUEUE_H
+
+#include "list.h" // struct list_head
+
+#define MAX_CLOCK 0x7fffffffffffffff
+
+#define MESSAGE_MIN 5
+#define MESSAGE_MAX 64
+#define MESSAGE_HEADER_SIZE  2
+#define MESSAGE_TRAILER_SIZE 3
+#define MESSAGE_POS_LEN 0
+#define MESSAGE_POS_SEQ 1
+#define MESSAGE_TRAILER_CRC  3
+#define MESSAGE_TRAILER_SYNC 1
+#define MESSAGE_PAYLOAD_MAX (MESSAGE_MAX - MESSAGE_MIN)
+#define MESSAGE_SEQ_MASK 0x0f
+#define MESSAGE_DEST 0x10
+#define MESSAGE_SYNC 0x7E
+
+struct queue_message {
+    int len;
+    uint8_t msg[MESSAGE_MAX];
+    union {
+        // Filled when on a command queue
+        struct {
+            uint64_t min_clock, req_clock;
+        };
+        // Filled when in sent/receive queues
+        struct {
+            double sent_time, receive_time;
+        };
+    };
+    struct list_node node;
+};
+
+struct queue_message *message_alloc_and_encode(uint32_t *data, int len);
+void message_queue_free(struct list_head *root);
+
+struct pull_queue_message {
+    uint8_t msg[MESSAGE_MAX];
+    int len;
+    double sent_time, receive_time;
+};
+
+struct serialqueue;
+struct serialqueue *serialqueue_alloc(int serial_fd, int write_only);
+void serialqueue_exit(struct serialqueue *sq);
+void serialqueue_free(struct serialqueue *sq);
+struct command_queue *serialqueue_alloc_commandqueue(void);
+void serialqueue_free_commandqueue(struct command_queue *cq);
+void serialqueue_send_batch(struct serialqueue *sq, struct command_queue *cq
+                            , struct list_head *msgs);
+void serialqueue_send(struct serialqueue *sq, struct command_queue *cq
+                      , uint8_t *msg, int len
+                      , uint64_t min_clock, uint64_t req_clock);
+void serialqueue_encode_and_send(struct serialqueue *sq, struct command_queue *cq
+                                 , uint32_t *data, int len
+                                 , uint64_t min_clock, uint64_t req_clock);
+void serialqueue_pull(struct serialqueue *sq, struct pull_queue_message *pqm);
+void serialqueue_set_baud_adjust(struct serialqueue *sq, double baud_adjust);
+void serialqueue_set_clock_est(struct serialqueue *sq, double est_clock
+                               , double last_ack_time, uint64_t last_ack_clock);
+void serialqueue_flush_ready(struct serialqueue *sq);
+void serialqueue_get_stats(struct serialqueue *sq, char *buf, int len);
+int serialqueue_extract_old(struct serialqueue *sq, int sentq
+                            , struct pull_queue_message *q, int max);
+
+#endif // serialqueue.h

klippy/stepcompress.c

@@ -0,0 +1,704 @@
+// Stepper pulse schedule compression
+//
+// Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+//
+// This file may be distributed under the terms of the GNU GPLv3 license.
+//
+// The goal of this code is to take a series of scheduled stepper
+// pulse times and compress them into a handful of commands that can
+// be efficiently transmitted and executed on a microcontroller (mcu).
+// The mcu accepts step pulse commands that take interval, count, and
+// add parameters such that 'count' pulses occur, with each step event
+// calculating the next step event time using:
+//  next_wake_time = last_wake_time + interval; interval += add
+// This code is writtin in C (instead of python) for processing
+// efficiency - the repetitive integer math is vastly faster in C.
+
+#include <math.h> // sqrt
+#include <stddef.h> // offsetof
+#include <stdint.h> // uint32_t
+#include <stdio.h> // fprintf
+#include <stdlib.h> // malloc
+#include <string.h> // memset
+#include "pyhelper.h" // errorf
+#include "serialqueue.h" // struct queue_message
+
+#define CHECK_LINES 1
+#define QUEUE_START_SIZE 1024
+
+struct stepcompress {
+    // Buffer management
+    uint64_t *queue, *queue_end, *queue_pos, *queue_next;
+    // Internal tracking
+    uint32_t max_error;
+    // Error checking
+    uint32_t errors;
+    // Message generation
+    uint64_t last_step_clock;
+    struct list_head msg_queue;
+    uint32_t queue_step_msgid, set_next_step_dir_msgid, oid;
+    int sdir, invert_sdir;
+};
+
+
+/****************************************************************
+ * Queue management
+ ****************************************************************/
+
+// Shuffle the internal queue to avoid having to allocate more ram
+static void
+clean_queue(struct stepcompress *sc)
+{
+    int in_use = sc->queue_next - sc->queue_pos;
+    memmove(sc->queue, sc->queue_pos, in_use * sizeof(*sc->queue));
+    sc->queue_pos = sc->queue;
+    sc->queue_next = sc->queue + in_use;
+}
+
+// Expand the internal queue of step times
+static void
+expand_queue(struct stepcompress *sc, int count)
+{
+    int alloc = sc->queue_end - sc->queue;
+    if (count + sc->queue_next - sc->queue_pos <= alloc) {
+        clean_queue(sc);
+        return;
+    }
+    int pos = sc->queue_pos - sc->queue;
+    int next = sc->queue_next - sc->queue;
+    if (!alloc)
+        alloc = QUEUE_START_SIZE;
+    while (next + count > alloc)
+        alloc *= 2;
+    sc->queue = realloc(sc->queue, alloc * sizeof(*sc->queue));
+    sc->queue_end = sc->queue + alloc;
+    sc->queue_pos = sc->queue + pos;
+    sc->queue_next = sc->queue + next;
+}
+
+
+/****************************************************************
+ * Step compression
+ ****************************************************************/
+
+#define DIV_UP(n,d) (((n) + (d) - 1) / (d))
+
+static inline int32_t
+idiv_up(int32_t n, int32_t d)
+{
+    return (n>=0) ? DIV_UP(n,d) : (n/d);
+}
+
+static inline int32_t
+idiv_down(int32_t n, int32_t d)
+{
+    return (n>=0) ? (n/d) : (n - d + 1) / d;
+}
+
+struct points {
+    int32_t minp, maxp;
+};
+
+// Given a requested step time, return the minimum and maximum
+// acceptable times
+static inline struct points
+minmax_point(struct stepcompress *sc, uint64_t *pos)
+{
+    uint32_t prevpoint = pos > sc->queue_pos ? *(pos-1) - sc->last_step_clock : 0;
+    uint32_t point = *pos - sc->last_step_clock;
+    uint32_t max_error = (point - prevpoint) / 2;
+    if (max_error > sc->max_error)
+        max_error = sc->max_error;
+    return (struct points){ point - max_error, point };
+}
+
+// The maximum add delta between two valid quadratic sequences of the
+// form "add*count*(count-1)/2 + interval*count" is "(6 + 4*sqrt(2)) *
+// maxerror / (count*count)".  The "6 + 4*sqrt(2)" is 11.65685, but
+// using 11 works well in practice.
+#define QUADRATIC_DEV 11
+
+struct step_move {
+    uint32_t interval;
+    uint16_t count;
+    int16_t add;
+};
+
+// Find a 'step_move' that covers a series of step times
+static struct step_move
+compress_bisect_add(struct stepcompress *sc)
+{
+    struct points point = minmax_point(sc, sc->queue_pos);
+    int32_t outer_mininterval = point.minp, outer_maxinterval = point.maxp;
+    int32_t add = 0, minadd = -0x8000, maxadd = 0x7fff;
+    int32_t bestinterval = 0, bestcount = 1, bestadd = 1, bestreach = INT32_MIN;
+    int32_t zerointerval = 0, zerocount = 0;
+
+    for (;;) {
+        // Find longest valid sequence with the given 'add'
+        struct points nextpoint;
+        int32_t nextmininterval = outer_mininterval;
+        int32_t nextmaxinterval = outer_maxinterval, interval = nextmaxinterval;
+        int32_t nextcount = 1;
+        for (;;) {
+            nextcount++;
+            if (nextcount > bestcount
+                && (&sc->queue_pos[nextcount-1] >= sc->queue_next
+                    || sc->queue_pos[nextcount-1] >= sc->last_step_clock+(3<<28)
+                    || nextcount > 65535)) {
+                int32_t count = nextcount - 1;
+                return (struct step_move){ interval, count, add };
+            }
+            nextpoint = minmax_point(sc, sc->queue_pos + nextcount - 1);
+            int32_t nextaddfactor = nextcount*(nextcount-1)/2;
+            int32_t c = add*nextaddfactor;
+            if (nextmininterval*nextcount < nextpoint.minp - c)
+                nextmininterval = DIV_UP(nextpoint.minp - c, nextcount);
+            if (nextmaxinterval*nextcount > nextpoint.maxp - c)
+                nextmaxinterval = (nextpoint.maxp - c) / nextcount;
+            if (nextmininterval > nextmaxinterval)
+                break;
+            interval = nextmaxinterval;
+        }
+
+        // Check if this is the best sequence found so far
+        int32_t count = nextcount - 1, addfactor = count*(count-1)/2;
+        int32_t reach = add*addfactor + interval*count;
+        if (reach > bestreach
+            || (reach == bestreach && interval > bestinterval)) {
+            bestinterval = interval;
+            bestcount = count;
+            bestadd = add;
+            bestreach = reach;
+            if (!add) {
+                zerointerval = interval;
+                zerocount = count;
+            }
+        }
+
+        // Check if a greater or lesser add could extend the sequence
+        int32_t nextaddfactor = nextcount*(nextcount-1)/2;
+        int32_t nextreach = add*nextaddfactor + interval*nextcount;
+        if (nextreach < nextpoint.minp) {
+            minadd = add + 1;
+            outer_maxinterval = nextmaxinterval;
+        } else {
+            maxadd = add - 1;
+            outer_mininterval = nextmininterval;
+        }
+
+        // The maximum valid deviation between two quadratic sequences
+        // can be calculated and used to further limit the add range.
+        if (count > 1) {
+            int32_t errdelta = sc->max_error*QUADRATIC_DEV / (count*count);
+            if (minadd < add - errdelta)
+                minadd = add - errdelta;
+            if (maxadd > add + errdelta)
+                maxadd = add + errdelta;
+        }
+
+        // See if next point would further limit the add range
+        int32_t c = outer_maxinterval * nextcount;
+        if (minadd*nextaddfactor < nextpoint.minp - c)
+            minadd = idiv_up(nextpoint.minp - c, nextaddfactor);
+        c = outer_mininterval * nextcount;
+        if (maxadd*nextaddfactor > nextpoint.maxp - c)
+            maxadd = idiv_down(nextpoint.maxp - c, nextaddfactor);
+
+        // Bisect valid add range and try again with new 'add'
+        if (minadd > maxadd)
+            break;
+        add = maxadd - (maxadd - minadd) / 4;
+    }
+    if (zerocount + zerocount/16 >= bestcount)
+        // Prefer add=0 if it's similar to the best found sequence
+        return (struct step_move){ zerointerval, zerocount, 0 };
+    return (struct step_move){ bestinterval, bestcount, bestadd };
+}
+
+
+/****************************************************************
+ * Step compress checking
+ ****************************************************************/
+
+// Verify that a given 'step_move' matches the actual step times
+static void
+check_line(struct stepcompress *sc, struct step_move move)
+{
+    if (!CHECK_LINES)
+        return;
+    if (move.count == 1) {
+        if (move.interval != (uint32_t)(*sc->queue_pos - sc->last_step_clock)
+            || *sc->queue_pos < sc->last_step_clock) {
+            errorf("Count 1 point out of range: %d %d %d"
+                   , move.interval, move.count, move.add);
+            sc->errors++;
+        }
+        return;
+    }
+    int err = 0;
+    if (!move.count || (!move.interval && !move.add)
+        || move.interval >= 0x80000000) {
+        errorf("Point out of range: %d %d %d"
+               , move.interval, move.count, move.add);
+        err++;
+    }
+    uint32_t interval = move.interval, p = 0;
+    uint16_t i;
+    for (i=0; i<move.count; i++) {
+        struct points point = minmax_point(sc, sc->queue_pos + i);
+        p += interval;
+        if (p < point.minp || p > point.maxp) {
+            errorf("Point %d of %d: %d not in %d:%d"
+                   , i+1, move.count, p, point.minp, point.maxp);
+            err++;
+        }
+        if (interval >= 0x80000000) {
+            errorf("Point %d of %d: interval overflow %d"
+                   , i+1, move.count, interval);
+            err++;
+        }
+        interval += move.add;
+    }
+    sc->errors += err;
+}
+
+
+/****************************************************************
+ * Step compress interface
+ ****************************************************************/
+
+#define likely(x)       __builtin_expect(!!(x), 1)
+
+// Wrapper around sqrt() to handle small negative numbers
+static double
+_safe_sqrt(double v)
+{
+    if (v > -0.001)
+        // Due to floating point truncation, it's possible to get a
+        // small negative number - treat it as zero.
+        return 0.;
+    return sqrt(v);
+}
+static inline double safe_sqrt(double v) {
+    return likely(v >= 0.) ? sqrt(v) : _safe_sqrt(v);
+}
+
+// Allocate a new 'stepcompress' object
+struct stepcompress *
+stepcompress_alloc(uint32_t max_error, uint32_t queue_step_msgid
+                   , uint32_t set_next_step_dir_msgid, uint32_t invert_sdir
+                   , uint32_t oid)
+{
+    struct stepcompress *sc = malloc(sizeof(*sc));
+    memset(sc, 0, sizeof(*sc));
+    sc->max_error = max_error;
+    list_init(&sc->msg_queue);
+    sc->queue_step_msgid = queue_step_msgid;
+    sc->set_next_step_dir_msgid = set_next_step_dir_msgid;
+    sc->oid = oid;
+    sc->sdir = -1;
+    sc->invert_sdir = !!invert_sdir;
+    return sc;
+}
+
+// Free memory associated with a 'stepcompress' object
+void
+stepcompress_free(struct stepcompress *sc)
+{
+    if (!sc)
+        return;
+    free(sc->queue);
+    message_queue_free(&sc->msg_queue);
+    free(sc);
+}
+
+// Convert previously scheduled steps into commands for the mcu
+static void
+stepcompress_flush(struct stepcompress *sc, uint64_t move_clock)
+{
+    if (sc->queue_pos >= sc->queue_next)
+        return;
+    while (move_clock > sc->last_step_clock) {
+        struct step_move move = compress_bisect_add(sc);
+        check_line(sc, move);
+
+        uint32_t msg[5] = {
+            sc->queue_step_msgid, sc->oid, move.interval, move.count, move.add
+        };
+        struct queue_message *qm = message_alloc_and_encode(msg, 5);
+        qm->min_clock = qm->req_clock = sc->last_step_clock;
+        if (move.count == 1 && sc->last_step_clock + (1<<27) < *sc->queue_pos) {
+            // Be careful with 32bit overflow
+            sc->last_step_clock = qm->req_clock = *sc->queue_pos;
+        } else {
+            uint32_t addfactor = move.count*(move.count-1)/2;
+            uint32_t ticks = move.add*addfactor + move.interval*move.count;
+            sc->last_step_clock += ticks;
+        }
+        list_add_tail(&qm->node, &sc->msg_queue);
+
+        if (sc->queue_pos + move.count >= sc->queue_next) {
+            sc->queue_pos = sc->queue_next = sc->queue;
+            break;
+        }
+        sc->queue_pos += move.count;
+    }
+}
+
+// Send the set_next_step_dir command
+static void
+set_next_step_dir(struct stepcompress *sc, int sdir)
+{
+    sc->sdir = sdir;
+    stepcompress_flush(sc, UINT64_MAX);
+    uint32_t msg[3] = {
+        sc->set_next_step_dir_msgid, sc->oid, sdir ^ sc->invert_sdir
+    };
+    struct queue_message *qm = message_alloc_and_encode(msg, 3);
+    qm->req_clock = sc->last_step_clock;
+    list_add_tail(&qm->node, &sc->msg_queue);
+}
+
+// Check if the internal queue needs to be expanded, and expand if so
+static inline void
+check_expand(struct stepcompress *sc, int sdir, int count)
+{
+    if (sdir != sc->sdir)
+        set_next_step_dir(sc, sdir);
+    if (sc->queue_next + count > sc->queue_end)
+        expand_queue(sc, count);
+}
+
+// Schedule a step event at the specified step_clock time
+void
+stepcompress_push(struct stepcompress *sc, double step_clock, int32_t sdir)
+{
+    sdir = !!sdir;
+    check_expand(sc, sdir, 1);
+    step_clock += 0.5;
+    *sc->queue_next++ = step_clock;
+}
+
+// Schedule 'steps' number of steps with a constant time between steps
+// using the formula: step_clock = clock_offset + step_num*factor
+int32_t
+stepcompress_push_factor(struct stepcompress *sc
+                         , double steps, double step_offset
+                         , double clock_offset, double factor)
+{
+    // Calculate number of steps to take
+    int sdir = 1;
+    if (steps < 0) {
+        sdir = 0;
+        steps = -steps;
+        step_offset = -step_offset;
+    }
+    int count = steps + .5 - step_offset;
+    if (count <= 0 || count > 1000000) {
+        if (count && steps)
+            errorf("push_factor invalid count %d %f %f %f %f"
+                   , sc->oid, steps, step_offset, clock_offset, factor);
+        return 0;
+    }
+    check_expand(sc, sdir, count);
+
+    // Calculate each step time
+    uint64_t *qn = sc->queue_next, *end = &qn[count];
+    clock_offset += 0.5;
+    double pos = step_offset + .5;
+    while (qn < end) {
+        *qn++ = clock_offset + pos*factor;
+        pos += 1.0;
+    }
+    sc->queue_next = qn;
+    return sdir ? count : -count;
+}
+
+// Schedule 'steps' number of steps using the formula:
+//  step_clock = clock_offset + sqrt(step_num*factor + sqrt_offset)
+int32_t
+stepcompress_push_sqrt(struct stepcompress *sc, double steps, double step_offset
+                       , double clock_offset, double sqrt_offset, double factor)
+{
+    // Calculate number of steps to take
+    int sdir = 1;
+    if (steps < 0) {
+        sdir = 0;
+        steps = -steps;
+        step_offset = -step_offset;
+    }
+    int count = steps + .5 - step_offset;
+    if (count <= 0 || count > 1000000) {
+        if (count && steps)
+            errorf("push_sqrt invalid count %d %f %f %f %f %f"
+                   , sc->oid, steps, step_offset, clock_offset, sqrt_offset
+                   , factor);
+        return 0;
+    }
+    check_expand(sc, sdir, count);
+
+    // Calculate each step time
+    uint64_t *qn = sc->queue_next, *end = &qn[count];
+    clock_offset += 0.5;
+    double pos = step_offset + .5 + sqrt_offset/factor;
+    while (qn < end) {
+        double v = safe_sqrt(pos*factor);
+        *qn++ = clock_offset + (factor >= 0. ? v : -v);
+        pos += 1.0;
+    }
+    sc->queue_next = qn;
+    return sdir ? count : -count;
+}
+
+// Schedule 'count' number of steps using the delta kinematic const speed
+int32_t
+stepcompress_push_delta_const(
+    struct stepcompress *sc, double clock_offset, double dist, double start_pos
+    , double inv_velocity, double step_dist
+    , double height, double closestxy_d, double closest_height2, double movez_r)
+{
+    // Calculate number of steps to take
+    double movexy_r = movez_r ? sqrt(1. - movez_r*movez_r) : 1.;
+    double reldist = closestxy_d - movexy_r*dist;
+    double end_height = safe_sqrt(closest_height2 - reldist*reldist);
+    int count = (end_height - height + movez_r*dist) / step_dist + .5;
+    if (count <= 0 || count > 1000000) {
+        if (count)
+            errorf("push_delta_const invalid count %d %d %f %f %f %f %f %f %f %f"
+                   , sc->oid, count, clock_offset, dist, step_dist, start_pos
+                   , closest_height2, height, movez_r, inv_velocity);
+        return 0;
+    }
+    check_expand(sc, step_dist > 0., count);
+
+    // Calculate each step time
+    uint64_t *qn = sc->queue_next, *end = &qn[count];
+    clock_offset += 0.5;
+    start_pos += movexy_r*closestxy_d;
+    height += .5 * step_dist;
+    if (!movez_r) {
+        // Optmized case for common XY only moves (no Z movement)
+        while (qn < end) {
+            double v = safe_sqrt(closest_height2 - height*height);
+            double pos = start_pos + (step_dist > 0. ? -v : v);
+            *qn++ = clock_offset + pos * inv_velocity;
+            height += step_dist;
+        }
+    } else if (!movexy_r) {
+        // Optmized case for Z only moves
+        double v = (step_dist > 0. ? -end_height : end_height);
+        while (qn < end) {
+            double pos = start_pos + movez_r*height + v;
+            *qn++ = clock_offset + pos * inv_velocity;
+            height += step_dist;
+        }
+    } else {
+        // General case (handles XY+Z moves)
+        while (qn < end) {
+            double relheight = movexy_r*height - movez_r*closestxy_d;
+            double v = safe_sqrt(closest_height2 - relheight*relheight);
+            double pos = start_pos + movez_r*height + (step_dist > 0. ? -v : v);
+            *qn++ = clock_offset + pos * inv_velocity;
+            height += step_dist;
+        }
+    }
+    sc->queue_next = qn;
+    return step_dist > 0. ? count : -count;
+}
+
+// Schedule 'count' number of steps using delta kinematic acceleration
+int32_t
+stepcompress_push_delta_accel(
+    struct stepcompress *sc, double clock_offset, double dist, double start_pos
+    , double accel_multiplier, double step_dist
+    , double height, double closestxy_d, double closest_height2, double movez_r)
+{
+    // Calculate number of steps to take
+    double movexy_r = movez_r ? sqrt(1. - movez_r*movez_r) : 1.;
+    double reldist = closestxy_d - movexy_r*dist;
+    double end_height = safe_sqrt(closest_height2 - reldist*reldist);
+    int count = (end_height - height + movez_r*dist) / step_dist + .5;
+    if (count <= 0 || count > 1000000) {
+        if (count)
+            errorf("push_delta_accel invalid count %d %d %f %f %f %f %f %f %f %f"
+                   , sc->oid, count, clock_offset, dist, step_dist, start_pos
+                   , closest_height2, height, movez_r, accel_multiplier);
+        return 0;
+    }
+    check_expand(sc, step_dist > 0., count);
+
+    // Calculate each step time
+    uint64_t *qn = sc->queue_next, *end = &qn[count];
+    clock_offset += 0.5;
+    start_pos += movexy_r*closestxy_d;
+    height += .5 * step_dist;
+    while (qn < end) {
+        double relheight = movexy_r*height - movez_r*closestxy_d;
+        double v = safe_sqrt(closest_height2 - relheight*relheight);
+        double pos = start_pos + movez_r*height + (step_dist > 0. ? -v : v);
+        v = safe_sqrt(pos * accel_multiplier);
+        *qn++ = clock_offset + (accel_multiplier >= 0. ? v : -v);
+        height += step_dist;
+    }
+    sc->queue_next = qn;
+    return step_dist > 0. ? count : -count;
+}
+
+// Reset the internal state of the stepcompress object
+void
+stepcompress_reset(struct stepcompress *sc, uint64_t last_step_clock)
+{
+    stepcompress_flush(sc, UINT64_MAX);
+    sc->last_step_clock = last_step_clock;
+    sc->sdir = -1;
+}
+
+// Queue an mcu command to go out in order with stepper commands
+void
+stepcompress_queue_msg(struct stepcompress *sc, uint32_t *data, int len)
+{
+    stepcompress_flush(sc, UINT64_MAX);
+
+    struct queue_message *qm = message_alloc_and_encode(data, len);
+    qm->req_clock = sc->last_step_clock;
+    list_add_tail(&qm->node, &sc->msg_queue);
+}
+
+// Return the count of internal errors found
+uint32_t
+stepcompress_get_errors(struct stepcompress *sc)
+{
+    return sc->errors;
+}
+
+
+/****************************************************************
+ * Step compress synchronization
+ ****************************************************************/
+
+// The steppersync object is used to synchronize the output of mcu
+// step commands.  The mcu can only queue a limited number of step
+// commands - this code tracks when items on the mcu step queue become
+// free so that new commands can be transmitted.  It also ensures the
+// mcu step queue is ordered between steppers so that no stepper
+// starves the other steppers of space in the mcu step queue.
+
+struct steppersync {
+    // Serial port
+    struct serialqueue *sq;
+    struct command_queue *cq;
+    // Storage for associated stepcompress objects
+    struct stepcompress **sc_list;
+    int sc_num;
+    // Storage for list of pending move clocks
+    uint64_t *move_clocks;
+    int num_move_clocks;
+};
+
+// Allocate a new 'steppersync' object
+struct steppersync *
+steppersync_alloc(struct serialqueue *sq, struct stepcompress **sc_list
+                  , int sc_num, int move_num)
+{
+    struct steppersync *ss = malloc(sizeof(*ss));
+    memset(ss, 0, sizeof(*ss));
+    ss->sq = sq;
+    ss->cq = serialqueue_alloc_commandqueue();
+
+    ss->sc_list = malloc(sizeof(*sc_list)*sc_num);
+    memcpy(ss->sc_list, sc_list, sizeof(*sc_list)*sc_num);
+    ss->sc_num = sc_num;
+
+    ss->move_clocks = malloc(sizeof(*ss->move_clocks)*move_num);
+    memset(ss->move_clocks, 0, sizeof(*ss->move_clocks)*move_num);
+    ss->num_move_clocks = move_num;
+
+    return ss;
+}
+
+// Free memory associated with a 'steppersync' object
+void
+steppersync_free(struct steppersync *ss)
+{
+    if (!ss)
+        return;
+    free(ss->sc_list);
+    free(ss->move_clocks);
+    serialqueue_free_commandqueue(ss->cq);
+    free(ss);
+}
+
+// Implement a binary heap algorithm to track when the next available
+// 'struct move' in the mcu will be available
+static void
+heap_replace(struct steppersync *ss, uint64_t req_clock)
+{
+    uint64_t *mc = ss->move_clocks;
+    int nmc = ss->num_move_clocks, pos = 0;
+    for (;;) {
+        int child1_pos = 2*pos+1, child2_pos = 2*pos+2;
+        uint64_t child2_clock = child2_pos < nmc ? mc[child2_pos] : UINT64_MAX;
+        uint64_t child1_clock = child1_pos < nmc ? mc[child1_pos] : UINT64_MAX;
+        if (req_clock <= child1_clock && req_clock <= child2_clock) {
+            mc[pos] = req_clock;
+            break;
+        }
+        if (child1_clock < child2_clock) {
+            mc[pos] = child1_clock;
+            pos = child1_pos;
+        } else {
+            mc[pos] = child2_clock;
+            pos = child2_pos;
+        }
+    }
+}
+
+// Find and transmit any scheduled steps prior to the given 'move_clock'
+void
+steppersync_flush(struct steppersync *ss, uint64_t move_clock)
+{
+    // Flush each stepcompress to the specified move_clock
+    int i;
+    for (i=0; i<ss->sc_num; i++)
+        stepcompress_flush(ss->sc_list[i], move_clock);
+
+    // Order commands by the reqclock of each pending command
+    struct list_head msgs;
+    list_init(&msgs);
+    for (;;) {
+        // Find message with lowest reqclock
+        uint64_t req_clock = MAX_CLOCK;
+        struct queue_message *qm = NULL;
+        for (i=0; i<ss->sc_num; i++) {
+            struct stepcompress *sc = ss->sc_list[i];
+            if (!list_empty(&sc->msg_queue)) {
+                struct queue_message *m = list_first_entry(
+                    &sc->msg_queue, struct queue_message, node);
+                if (m->req_clock < req_clock) {
+                    qm = m;
+                    req_clock = m->req_clock;
+                }
+            }
+        }
+        if (!qm || (qm->min_clock && req_clock > move_clock))
+            break;
+
+        uint64_t next_avail = ss->move_clocks[0];
+        if (qm->min_clock)
+            // The qm->min_clock field is overloaded to indicate that
+            // the command uses the 'move queue' and to store the time
+            // that move queue item becomes available.
+            heap_replace(ss, qm->min_clock);
+        // Reset the min_clock to its normal meaning (minimum transmit time)
+        qm->min_clock = next_avail;
+
+        // Batch this command
+        list_del(&qm->node);
+        list_add_tail(&qm->node, &msgs);
+    }
+
+    // Transmit commands
+    if (!list_empty(&msgs))
+        serialqueue_send_batch(ss->sq, ss->cq, &msgs);
+}

klippy/stepper.py

@@ -0,0 +1,101 @@
+# Printer stepper support
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import math, logging
+import homing
+
+class PrinterStepper:
+    def __init__(self, printer, config, name):
+        self.printer = printer
+        self.config = config
+        self.name = name
+        self.mcu_stepper = self.mcu_enable = self.mcu_endstop = None
+
+        self.step_dist = config.getfloat('step_distance')
+        self.inv_step_dist = 1. / self.step_dist
+        self.min_stop_interval = 0.
+
+        self.homing_speed = config.getfloat('homing_speed', 5.0)
+        self.homing_positive_dir = config.getboolean(
+            'homing_positive_dir', False)
+        self.homing_retract_dist = config.getfloat('homing_retract_dist', 5.)
+        self.homing_stepper_phases = config.getint('homing_stepper_phases', None)
+        self.homing_endstop_phase = config.getint('homing_endstop_phase', None)
+        endstop_accuracy = config.getfloat('homing_endstop_accuracy', None)
+        self.homing_endstop_accuracy = None
+        if self.homing_stepper_phases:
+            if endstop_accuracy is None:
+                self.homing_endstop_accuracy = self.homing_stepper_phases//2 - 1
+            elif self.homing_endstop_phase is not None:
+                self.homing_endstop_accuracy = int(math.ceil(
+                    endstop_accuracy * self.inv_step_dist / 2.))
+            else:
+                self.homing_endstop_accuracy = int(math.ceil(
+                    endstop_accuracy * self.inv_step_dist))
+            if self.homing_endstop_accuracy >= self.homing_stepper_phases/2:
+                logging.info("Endstop for %s is not accurate enough for stepper"
+                             " phase adjustment" % (self.config.section,))
+                self.homing_stepper_phases = None
+        self.position_min = self.position_endstop = self.position_max = None
+        if config.get('endstop_pin', None) is not None:
+            self.position_min = config.getfloat('position_min', 0.)
+            self.position_endstop = config.getfloat('position_endstop')
+            self.position_max = config.getfloat('position_max', 0.)
+
+        self.need_motor_enable = True
+    def set_max_jerk(self, max_halt_velocity, max_accel):
+        jc = max_halt_velocity / max_accel
+        inv_max_step_accel = self.step_dist / max_accel
+        self.min_stop_interval = (math.sqrt(3.*inv_max_step_accel + jc**2)
+                                  - math.sqrt(inv_max_step_accel + jc**2))
+    def build_config(self):
+        max_error = self.config.getfloat('max_error', 0.000050)
+        step_pin = self.config.get('step_pin')
+        dir_pin = self.config.get('dir_pin')
+        min_stop_interval = max(0., self.min_stop_interval - max_error)
+        mcu = self.printer.mcu
+        self.mcu_stepper = mcu.create_stepper(
+            step_pin, dir_pin, min_stop_interval, max_error)
+        enable_pin = self.config.get('enable_pin', None)
+        if enable_pin is not None:
+            self.mcu_enable = mcu.create_digital_out(enable_pin, 0)
+        endstop_pin = self.config.get('endstop_pin', None)
+        if endstop_pin is not None:
+            self.mcu_endstop = mcu.create_endstop(endstop_pin, self.mcu_stepper)
+    def motor_enable(self, move_time, enable=0):
+        if enable and self.need_motor_enable:
+            mcu_time = self.mcu_stepper.print_to_mcu_time(move_time)
+            self.mcu_stepper.reset_step_clock(mcu_time)
+        if (self.mcu_enable is not None
+            and self.mcu_enable.get_last_setting() != enable):
+            mcu_time = self.mcu_enable.print_to_mcu_time(move_time)
+            self.mcu_enable.set_digital(mcu_time, enable)
+        self.need_motor_enable = not enable
+    def enable_endstop_checking(self, move_time, step_time):
+        mcu_time = self.mcu_endstop.print_to_mcu_time(move_time)
+        self.mcu_endstop.home_start(mcu_time, step_time)
+        return self.mcu_endstop
+    def query_endstop(self, print_time):
+        mcu_time = self.mcu_endstop.print_to_mcu_time(print_time)
+        self.mcu_endstop.query_endstop(mcu_time)
+        return self.mcu_endstop
+    def get_homed_offset(self):
+        if not self.homing_stepper_phases or self.need_motor_enable:
+            return 0
+        pos = self.mcu_stepper.get_mcu_position()
+        pos %= self.homing_stepper_phases
+        if self.homing_endstop_phase is None:
+            logging.info("Setting %s endstop phase to %d" % (
+                self.config.section, pos))
+            self.homing_endstop_phase = pos
+            return 0
+        delta = (pos - self.homing_endstop_phase) % self.homing_stepper_phases
+        if delta >= self.homing_stepper_phases - self.homing_endstop_accuracy:
+            delta -= self.homing_stepper_phases
+        elif delta > self.homing_endstop_accuracy:
+            raise homing.EndstopError(
+                "Endstop %s incorrect phase (got %d vs %d)" % (
+                    self.name, pos, self.homing_endstop_phase))
+        return delta

klippy/toolhead.py

@@ -0,0 +1,293 @@
+# Code for coordinating events on the printer toolhead
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+import math, logging, time
+import cartesian, delta
+
+EXTRUDE_DIFF_IGNORE = 1.02
+
+# Common suffixes: _d is distance (in mm), _v is velocity (in
+#   mm/second), _t is time (in seconds), _r is ratio (scalar between
+#   0.0 and 1.0)
+
+# Class to track each move request
+class Move:
+    def __init__(self, toolhead, start_pos, end_pos, speed, accel):
+        self.toolhead = toolhead
+        self.start_pos = tuple(start_pos)
+        self.end_pos = tuple(end_pos)
+        self.accel = accel
+        self.do_calc_junction = True
+        self.axes_d = axes_d = [end_pos[i] - start_pos[i] for i in (0, 1, 2, 3)]
+        if axes_d[2]:
+            # Move with Z
+            move_d = math.sqrt(sum([d*d for d in axes_d[:3]]))
+            self.do_calc_junction = False
+        else:
+            move_d = math.sqrt(axes_d[0]**2 + axes_d[1]**2)
+            if not move_d:
+                # Extrude only move
+                move_d = abs(axes_d[3])
+                if not move_d:
+                    # No move
+                    self.move_d = 0.
+                    return
+                self.do_calc_junction = False
+        self.move_d = move_d
+        self.extrude_r = axes_d[3] / move_d
+        # Junction speeds are velocities squared.  The junction_delta
+        # is the maximum amount of this squared-velocity that can
+        # change in this move.
+        self.junction_max = speed**2
+        self.junction_delta = 2.0 * move_d * accel
+        self.junction_start_max = 0.
+    def limit_speed(self, speed, accel):
+        self.junction_max = min(self.junction_max, speed**2)
+        self.accel = min(self.accel, accel)
+        self.junction_delta = 2.0 * self.move_d * self.accel
+    def calc_junction(self, prev_move):
+        if not self.do_calc_junction or not prev_move.do_calc_junction:
+            return
+        # Find max junction_start_velocity between two moves
+        if (self.extrude_r > prev_move.extrude_r * EXTRUDE_DIFF_IGNORE
+            or prev_move.extrude_r > self.extrude_r * EXTRUDE_DIFF_IGNORE):
+            # Extrude ratio between moves is too different
+            return
+        self.extrude_r = prev_move.extrude_r
+        # Find max velocity using approximated centripetal velocity as
+        # described at:
+        # https://onehossshay.wordpress.com/2011/09/24/improving_grbl_cornering_algorithm/
+        junction_cos_theta = -((self.axes_d[0] * prev_move.axes_d[0]
+                                + self.axes_d[1] * prev_move.axes_d[1])
+                               / (self.move_d * prev_move.move_d))
+        if junction_cos_theta > 0.999999:
+            return
+        junction_cos_theta = max(junction_cos_theta, -0.999999)
+        sin_theta_d2 = math.sqrt(0.5*(1.0-junction_cos_theta))
+        R = self.toolhead.junction_deviation * sin_theta_d2 / (1. - sin_theta_d2)
+        self.junction_start_max = min(
+            R * self.accel, self.junction_max, prev_move.junction_max
+            , prev_move.junction_start_max + prev_move.junction_delta)
+    def process(self, junction_start, junction_cruise, junction_end
+                , cornering_min, cornering_max):
+        # Determine accel, cruise, and decel portions of the move distance
+        inv_junction_delta = 1. / self.junction_delta
+        accel_r = (junction_cruise-junction_start) * inv_junction_delta
+        decel_r = (junction_cruise-junction_end) * inv_junction_delta
+        cruise_r = 1. - accel_r - decel_r
+        self.accel_r, self.cruise_r, self.decel_r = accel_r, cruise_r, decel_r
+        # Determine move velocities
+        start_v = math.sqrt(junction_start)
+        cruise_v = math.sqrt(junction_cruise)
+        end_v = math.sqrt(junction_end)
+        self.start_v, self.cruise_v, self.end_v = start_v, cruise_v, end_v
+        self.corner_min = math.sqrt(cornering_min)
+        self.corner_max = math.sqrt(cornering_max)
+        # Determine time spent in each portion of move (time is the
+        # distance divided by average velocity)
+        accel_t = accel_r * self.move_d / ((start_v + cruise_v) * 0.5)
+        cruise_t = cruise_r * self.move_d / cruise_v
+        decel_t = decel_r * self.move_d / ((end_v + cruise_v) * 0.5)
+        self.accel_t, self.cruise_t, self.decel_t = accel_t, cruise_t, decel_t
+        # Generate step times for the move
+        next_move_time = self.toolhead.get_next_move_time()
+        self.toolhead.kin.move(next_move_time, self)
+        if self.axes_d[3]:
+            self.toolhead.extruder.move(next_move_time, self)
+        self.toolhead.update_move_time(accel_t + cruise_t + decel_t)
+
+# Class to track a list of pending move requests and to facilitate
+# "look-ahead" across moves to reduce acceleration between moves.
+class MoveQueue:
+    def __init__(self):
+        self.queue = []
+        self.junction_flush = 0.
+    def reset(self):
+        del self.queue[:]
+    def flush(self, lazy=False):
+        flush_count = len(self.queue)
+        move_info = [None] * flush_count
+        # Traverse queue from last to first move and determine maximum
+        # junction speed assuming the robot comes to a complete stop
+        # after the last move.
+        next_junction_end = cornering_min = cornering_max = 0.
+        for i in range(flush_count-1, -1, -1):
+            move = self.queue[i]
+            reachable_start = next_junction_end + move.junction_delta
+            junction_start = min(move.junction_start_max, reachable_start)
+            junction_cruise = min((junction_start + reachable_start) * .5
+                                  , move.junction_max)
+            move_info[i] = (junction_start, junction_cruise, next_junction_end
+                            , cornering_min, cornering_max)
+            if reachable_start > junction_start:
+                cornering_min = junction_start
+                if junction_start + move.junction_delta > next_junction_end:
+                    cornering_max = junction_cruise
+                    if lazy:
+                        flush_count = i
+                        lazy = False
+            next_junction_end = junction_start
+        if lazy:
+            flush_count = 0
+        # Generate step times for all moves ready to be flushed
+        for i in range(flush_count):
+            self.queue[i].process(*move_info[i])
+        # Remove processed moves from the queue
+        del self.queue[:flush_count]
+        if self.queue:
+            self.junction_flush = 2. * self.queue[-1].junction_max
+    def add_move(self, move):
+        self.queue.append(move)
+        if len(self.queue) == 1:
+            self.junction_flush = 2. * move.junction_max
+            return
+        move.calc_junction(self.queue[-2])
+        self.junction_flush -= move.junction_delta
+        if self.junction_flush <= 0.:
+            # There are enough queued moves to return to zero velocity
+            # from the first move's maximum possible velocity, so at
+            # least one move can be flushed.
+            self.flush(lazy=True)
+
+STALL_TIME = 0.100
+
+# Main code to track events (and their timing) on the printer toolhead
+class ToolHead:
+    def __init__(self, printer, config):
+        self.printer = printer
+        self.reactor = printer.reactor
+        self.extruder = printer.objects.get('extruder')
+        kintypes = {'cartesian': cartesian.CartKinematics,
+                    'delta': delta.DeltaKinematics}
+        self.kin = config.getchoice('kinematics', kintypes)(printer, config)
+        self.max_speed = config.getfloat('max_velocity')
+        self.max_accel = config.getfloat('max_accel')
+        self.junction_deviation = config.getfloat('junction_deviation', 0.02)
+        self.move_queue = MoveQueue()
+        self.commanded_pos = [0., 0., 0., 0.]
+        # Print time tracking
+        self.buffer_time_high = config.getfloat('buffer_time_high', 5.000)
+        self.buffer_time_low = config.getfloat('buffer_time_low', 0.150)
+        self.move_flush_time = config.getfloat('move_flush_time', 0.050)
+        self.motor_off_delay = config.getfloat('motor_off_time', 60.000)
+        self.print_time = 0.
+        self.need_check_stall = -1.
+        self.print_time_stall = 0
+        self.motor_off_time = self.reactor.NEVER
+        self.flush_timer = self.reactor.register_timer(self._flush_handler)
+    def build_config(self):
+        self.kin.set_max_jerk(0.005 * self.max_accel, self.max_accel) # XXX
+        self.kin.build_config()
+    # Print time tracking
+    def update_move_time(self, movetime):
+        self.print_time += movetime
+        flush_to_time = self.print_time - self.move_flush_time
+        self.printer.mcu.flush_moves(flush_to_time)
+    def get_next_move_time(self):
+        if not self.print_time:
+            self.print_time = self.buffer_time_low + STALL_TIME
+            curtime = time.time()
+            self.printer.mcu.set_print_start_time(curtime)
+            self.reactor.update_timer(self.flush_timer, self.reactor.NOW)
+        return self.print_time
+    def get_last_move_time(self):
+        self.move_queue.flush()
+        return self.get_next_move_time()
+    def reset_motor_off_time(self, eventtime):
+        self.motor_off_time = eventtime + self.motor_off_delay
+    def reset_print_time(self):
+        self.move_queue.flush()
+        self.printer.mcu.flush_moves(self.print_time)
+        self.print_time = 0.
+        self.need_check_stall = -1.
+        self.reset_motor_off_time(time.time())
+        self.reactor.update_timer(self.flush_timer, self.motor_off_time)
+    def _check_stall(self):
+        if not self.print_time:
+            # XXX - find better way to flush initial move_queue items
+            if self.move_queue.queue:
+                self.reactor.update_timer(self.flush_timer, time.time() + 0.100)
+            return
+        eventtime = time.time()
+        while 1:
+            buffer_time = self.printer.mcu.get_print_buffer_time(
+                eventtime, self.print_time)
+            stall_time = buffer_time - self.buffer_time_high
+            if stall_time <= 0.:
+                break
+            eventtime = self.reactor.pause(eventtime + stall_time)
+            if not self.print_time:
+                return
+        self.need_check_stall = self.print_time - stall_time + 0.100
+    def _flush_handler(self, eventtime):
+        try:
+            if not self.print_time:
+                self.move_queue.flush()
+                if not self.print_time:
+                    if eventtime >= self.motor_off_time:
+                        self.motor_off()
+                        self.reset_print_time()
+                        self.motor_off_time = self.reactor.NEVER
+                    return self.motor_off_time
+            print_time = self.print_time
+            buffer_time = self.printer.mcu.get_print_buffer_time(
+                eventtime, print_time)
+            if buffer_time > self.buffer_time_low:
+                return eventtime + buffer_time - self.buffer_time_low
+            self.move_queue.flush()
+            if print_time != self.print_time:
+                self.print_time_stall += 1
+                self.dwell(self.buffer_time_low + STALL_TIME)
+                return self.reactor.NOW
+            self.reset_print_time()
+            return self.motor_off_time
+        except:
+            logging.exception("Exception in flush_handler")
+            self.force_shutdown()
+    def stats(self, eventtime):
+        buffer_time = 0.
+        if self.print_time:
+            buffer_time = self.printer.mcu.get_print_buffer_time(
+                eventtime, self.print_time)
+        return "print_time=%.3f buffer_time=%.3f print_time_stall=%d" % (
+            self.print_time, buffer_time, self.print_time_stall)
+    # Movement commands
+    def get_position(self):
+        return list(self.commanded_pos)
+    def set_position(self, newpos):
+        self.move_queue.flush()
+        self.commanded_pos[:] = newpos
+        self.kin.set_position(newpos)
+    def move(self, newpos, speed):
+        speed = min(speed, self.max_speed)
+        move = Move(self, self.commanded_pos, newpos, speed, self.max_accel)
+        if not move.move_d:
+            return
+        self.kin.check_move(move)
+        if move.axes_d[3]:
+            self.extruder.check_move(move)
+        self.commanded_pos[:] = newpos
+        self.move_queue.add_move(move)
+        if self.print_time > self.need_check_stall:
+            self._check_stall()
+    def home(self, homing_state):
+        self.kin.home(homing_state)
+    def dwell(self, delay):
+        self.get_last_move_time()
+        self.update_move_time(delay)
+        self._check_stall()
+    def motor_off(self):
+        self.dwell(STALL_TIME)
+        last_move_time = self.get_last_move_time()
+        self.kin.motor_off(last_move_time)
+        self.extruder.motor_off(last_move_time)
+        self.dwell(STALL_TIME)
+        logging.debug('; Max time of %f' % (last_move_time,))
+    def query_endstops(self):
+        last_move_time = self.get_last_move_time()
+        return self.kin.query_endstops(last_move_time)
+    def force_shutdown(self):
+        self.printer.mcu.force_shutdown()
+        self.move_queue.reset()

klippy/util.py

@@ -0,0 +1,38 @@
+# Low level unix utility functions
+#
+# Copyright (C) 2016  Kevin O'Connor <kevin@koconnor.net>
+#
+# This file may be distributed under the terms of the GNU GPLv3 license.
+
+import os, pty, fcntl, termios, signal
+
+# Return the SIGINT interrupt handler back to the OS default
+def fix_sigint():
+    signal.signal(signal.SIGINT, signal.SIG_DFL)
+fix_sigint()
+
+# Set a file-descriptor as non-blocking
+def set_nonblock(fd):
+    fcntl.fcntl(fd, fcntl.F_SETFL
+                , fcntl.fcntl(fd, fcntl.F_GETFL) | os.O_NONBLOCK)
+
+# Clear HUPCL flag
+def clear_hupcl(fd):
+    attrs = termios.tcgetattr(fd)
+    attrs[2] = attrs[2] & ~termios.HUPCL
+    termios.tcsetattr(fd, termios.TCSADRAIN, attrs)
+
+# Support for creating a pseudo-tty for emulating a serial port
+def create_pty(ptyname):
+    mfd, sfd = pty.openpty()
+    try:
+        os.unlink(ptyname)
+    except os.error:
+        pass
+    os.symlink(os.ttyname(sfd), ptyname)
+    fcntl.fcntl(mfd, fcntl.F_SETFL
+                , fcntl.fcntl(mfd, fcntl.F_GETFL) | os.O_NONBLOCK)
+    old = termios.tcgetattr(mfd)
+    old[3] = old[3] & ~termios.ECHO
+    termios.tcsetattr(mfd, termios.TCSADRAIN, old)
+    return mfd

lib/README

@@ -0,0 +1,12 @@
+This directory contains external library code.
+
+The pjrc_usb_serial directory contains code from:
+  http://www.pjrc.com/teensy/usb_serial.html
+version 1.7 (extracted on 20160605). It has been modified to compile
+on recent versions of gcc. See usb_serial.patch for the modifications.
+
+The cmsis-sam3x8e directory contains code from the Arduino project:
+  https://www.arduino.cc/
+version 1.5.1 (extracted on 20160608).  It has been modified to
+compile with gcc's LTO feature. See cmsis-sam3x8e.patch for the
+modifications.

lib/cmsis-sam3x8e/cmsis-include/core_cmFunc.h

@@ -0,0 +1,609 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V2.10
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+static __INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+static __INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+static __INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+static __INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

lib/cmsis-sam3x8e/cmsis-include/core_cmInstr.h

@@ -0,0 +1,585 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz 
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+  
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

lib/cmsis-sam3x8e/cmsis-sam3x8e.patch

@@ -0,0 +1,11 @@
+--- source/gcc/startup_sam3xa.c.orig	2016-06-14 14:20:43.166209461 -0400
++++ source/gcc/startup_sam3xa.c	2016-06-14 14:00:57.497137169 -0400
+@@ -129,7 +129,7 @@
+ void CAN1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+ 
+ /* Exception Table */
+-__attribute__ ((section(".vectors")))
++__attribute__ ((section(".vectors"))) __attribute__((externally_visible))
+ const DeviceVectors exception_table = {
+ 
+ 	/* Configure Initial Stack Pointer, using linker-generated symbols */

lib/cmsis-sam3x8e/include/component/component_adc.h

@@ -0,0 +1,504 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_ADC_COMPONENT_
+#define _SAM3XA_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_ADC Analog-to-digital Converter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg Reserved1[1];
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[2];
+  RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  RwReg ADC_CGR;       /**< \brief (Adc Offset: 0x48) Channel Gain Register */
+  RwReg ADC_COR;       /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+  RoReg ADC_CDR[16];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
+  RoReg Reserved3[1];
+  RwReg ADC_ACR;       /**< \brief (Adc Offset: 0x94) Analog Control Register */
+  RoReg Reserved4[19];
+  RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved5[5];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RoReg Reserved6[2];
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RoReg Reserved7[2];
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External : ADCTRG */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
+#define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define   ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define   ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define   ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define   ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */
+#define   ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
+#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_CMPFILTER_Pos 12
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
+#define ADC_CGR_GAIN0_Pos 0
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
+#define ADC_CGR_GAIN1_Pos 2
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
+#define ADC_CGR_GAIN2_Pos 4
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
+#define ADC_CGR_GAIN3_Pos 6
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
+#define ADC_CGR_GAIN4_Pos 8
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
+#define ADC_CGR_GAIN5_Pos 10
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
+#define ADC_CGR_GAIN6_Pos 12
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
+#define ADC_CGR_GAIN7_Pos 14
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
+#define ADC_CGR_GAIN8_Pos 16
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
+#define ADC_CGR_GAIN9_Pos 18
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
+#define ADC_CGR_GAIN10_Pos 20
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
+#define ADC_CGR_GAIN11_Pos 22
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
+#define ADC_CGR_GAIN12_Pos 24
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
+#define ADC_CGR_GAIN13_Pos 26
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
+#define ADC_CGR_GAIN14_Pos 28
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
+#define ADC_CGR_GAIN15_Pos 30
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
+/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
+#define ADC_ACR_IBCTL_Pos 8
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_ADC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_can.h

@@ -0,0 +1,298 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CAN_COMPONENT_
+#define _SAM3XA_CAN_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Controller Area Network */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_CAN Controller Area Network */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief CanMb hardware registers */
+typedef struct {
+  RwReg  CAN_MMR;       /**< \brief (CanMb Offset: 0x0) Mailbox Mode Register */
+  RwReg  CAN_MAM;       /**< \brief (CanMb Offset: 0x4) Mailbox Acceptance Mask Register */
+  RwReg  CAN_MID;       /**< \brief (CanMb Offset: 0x8) Mailbox ID Register */
+  RwReg  CAN_MFID;      /**< \brief (CanMb Offset: 0xC) Mailbox Family ID Register */
+  RwReg  CAN_MSR;       /**< \brief (CanMb Offset: 0x10) Mailbox Status Register */
+  RwReg  CAN_MDL;       /**< \brief (CanMb Offset: 0x14) Mailbox Data Low Register */
+  RwReg  CAN_MDH;       /**< \brief (CanMb Offset: 0x18) Mailbox Data High Register */
+  RwReg  CAN_MCR;       /**< \brief (CanMb Offset: 0x1C) Mailbox Control Register */
+} CanMb;
+/** \brief Can hardware registers */
+#define CANMB_NUMBER 8
+typedef struct {
+  RwReg  CAN_MR;        /**< \brief (Can Offset: 0x0000) Mode Register */
+  WoReg  CAN_IER;       /**< \brief (Can Offset: 0x0004) Interrupt Enable Register */
+  WoReg  CAN_IDR;       /**< \brief (Can Offset: 0x0008) Interrupt Disable Register */
+  RoReg  CAN_IMR;       /**< \brief (Can Offset: 0x000C) Interrupt Mask Register */
+  RoReg  CAN_SR;        /**< \brief (Can Offset: 0x0010) Status Register */
+  RwReg  CAN_BR;        /**< \brief (Can Offset: 0x0014) Baudrate Register */
+  RoReg  CAN_TIM;       /**< \brief (Can Offset: 0x0018) Timer Register */
+  RoReg  CAN_TIMESTP;   /**< \brief (Can Offset: 0x001C) Timestamp Register */
+  RoReg  CAN_ECR;       /**< \brief (Can Offset: 0x0020) Error Counter Register */
+  WoReg  CAN_TCR;       /**< \brief (Can Offset: 0x0024) Transfer Command Register */
+  WoReg  CAN_ACR;       /**< \brief (Can Offset: 0x0028) Abort Command Register */
+  RoReg  Reserved1[46];
+  RwReg  CAN_WPMR;      /**< \brief (Can Offset: 0x00E4) Write Protect Mode Register */
+  RoReg  CAN_WPSR;      /**< \brief (Can Offset: 0x00E8) Write Protect Status Register */
+  RoReg  Reserved2[69];
+  CanMb  CAN_MB[CANMB_NUMBER]; /**< \brief (Can Offset: 0x200) MB = 0 .. 7 */
+} Can;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */
+#define CAN_MR_CANEN (0x1u << 0) /**< \brief (CAN_MR) CAN Controller Enable */
+#define CAN_MR_LPM (0x1u << 1) /**< \brief (CAN_MR) Disable/Enable Low Power Mode */
+#define CAN_MR_ABM (0x1u << 2) /**< \brief (CAN_MR) Disable/Enable Autobaud/Listen mode */
+#define CAN_MR_OVL (0x1u << 3) /**< \brief (CAN_MR) Disable/Enable Overload Frame */
+#define CAN_MR_TEOF (0x1u << 4) /**< \brief (CAN_MR) Timestamp messages at each end of Frame */
+#define CAN_MR_TTM (0x1u << 5) /**< \brief (CAN_MR) Disable/Enable Time Triggered Mode */
+#define CAN_MR_TIMFRZ (0x1u << 6) /**< \brief (CAN_MR) Enable Timer Freeze */
+#define CAN_MR_DRPT (0x1u << 7) /**< \brief (CAN_MR) Disable Repeat */
+#define CAN_MR_RXSYNC_Pos 24
+#define CAN_MR_RXSYNC_Msk (0x7u << CAN_MR_RXSYNC_Pos) /**< \brief (CAN_MR) Reception Synchronization Stage (not readable) */
+#define   CAN_MR_RXSYNC_DOUBLE_PP (0x0u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (2 Positive Edges) */
+#define   CAN_MR_RXSYNC_DOUBLE_PN (0x1u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) */
+#define   CAN_MR_RXSYNC_SINGLE_P (0x2u << 24) /**< \brief (CAN_MR) Rx Signal with Single Synchro Stage (Positive Edge) */
+#define   CAN_MR_RXSYNC_NONE (0x3u << 24) /**< \brief (CAN_MR) Rx Signal with No Synchro Stage */
+/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */
+#define CAN_IER_MB0 (0x1u << 0) /**< \brief (CAN_IER) Mailbox 0 Interrupt Enable */
+#define CAN_IER_MB1 (0x1u << 1) /**< \brief (CAN_IER) Mailbox 1 Interrupt Enable */
+#define CAN_IER_MB2 (0x1u << 2) /**< \brief (CAN_IER) Mailbox 2 Interrupt Enable */
+#define CAN_IER_MB3 (0x1u << 3) /**< \brief (CAN_IER) Mailbox 3 Interrupt Enable */
+#define CAN_IER_MB4 (0x1u << 4) /**< \brief (CAN_IER) Mailbox 4 Interrupt Enable */
+#define CAN_IER_MB5 (0x1u << 5) /**< \brief (CAN_IER) Mailbox 5 Interrupt Enable */
+#define CAN_IER_MB6 (0x1u << 6) /**< \brief (CAN_IER) Mailbox 6 Interrupt Enable */
+#define CAN_IER_MB7 (0x1u << 7) /**< \brief (CAN_IER) Mailbox 7 Interrupt Enable */
+#define CAN_IER_ERRA (0x1u << 16) /**< \brief (CAN_IER) Error Active Mode Interrupt Enable */
+#define CAN_IER_WARN (0x1u << 17) /**< \brief (CAN_IER) Warning Limit Interrupt Enable */
+#define CAN_IER_ERRP (0x1u << 18) /**< \brief (CAN_IER) Error Passive Mode Interrupt Enable */
+#define CAN_IER_BOFF (0x1u << 19) /**< \brief (CAN_IER) Bus Off Mode Interrupt Enable */
+#define CAN_IER_SLEEP (0x1u << 20) /**< \brief (CAN_IER) Sleep Interrupt Enable */
+#define CAN_IER_WAKEUP (0x1u << 21) /**< \brief (CAN_IER) Wakeup Interrupt Enable */
+#define CAN_IER_TOVF (0x1u << 22) /**< \brief (CAN_IER) Timer Overflow Interrupt Enable */
+#define CAN_IER_TSTP (0x1u << 23) /**< \brief (CAN_IER) TimeStamp Interrupt Enable */
+#define CAN_IER_CERR (0x1u << 24) /**< \brief (CAN_IER) CRC Error Interrupt Enable */
+#define CAN_IER_SERR (0x1u << 25) /**< \brief (CAN_IER) Stuffing Error Interrupt Enable */
+#define CAN_IER_AERR (0x1u << 26) /**< \brief (CAN_IER) Acknowledgment Error Interrupt Enable */
+#define CAN_IER_FERR (0x1u << 27) /**< \brief (CAN_IER) Form Error Interrupt Enable */
+#define CAN_IER_BERR (0x1u << 28) /**< \brief (CAN_IER) Bit Error Interrupt Enable */
+/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */
+#define CAN_IDR_MB0 (0x1u << 0) /**< \brief (CAN_IDR) Mailbox 0 Interrupt Disable */
+#define CAN_IDR_MB1 (0x1u << 1) /**< \brief (CAN_IDR) Mailbox 1 Interrupt Disable */
+#define CAN_IDR_MB2 (0x1u << 2) /**< \brief (CAN_IDR) Mailbox 2 Interrupt Disable */
+#define CAN_IDR_MB3 (0x1u << 3) /**< \brief (CAN_IDR) Mailbox 3 Interrupt Disable */
+#define CAN_IDR_MB4 (0x1u << 4) /**< \brief (CAN_IDR) Mailbox 4 Interrupt Disable */
+#define CAN_IDR_MB5 (0x1u << 5) /**< \brief (CAN_IDR) Mailbox 5 Interrupt Disable */
+#define CAN_IDR_MB6 (0x1u << 6) /**< \brief (CAN_IDR) Mailbox 6 Interrupt Disable */
+#define CAN_IDR_MB7 (0x1u << 7) /**< \brief (CAN_IDR) Mailbox 7 Interrupt Disable */
+#define CAN_IDR_ERRA (0x1u << 16) /**< \brief (CAN_IDR) Error Active Mode Interrupt Disable */
+#define CAN_IDR_WARN (0x1u << 17) /**< \brief (CAN_IDR) Warning Limit Interrupt Disable */
+#define CAN_IDR_ERRP (0x1u << 18) /**< \brief (CAN_IDR) Error Passive Mode Interrupt Disable */
+#define CAN_IDR_BOFF (0x1u << 19) /**< \brief (CAN_IDR) Bus Off Mode Interrupt Disable */
+#define CAN_IDR_SLEEP (0x1u << 20) /**< \brief (CAN_IDR) Sleep Interrupt Disable */
+#define CAN_IDR_WAKEUP (0x1u << 21) /**< \brief (CAN_IDR) Wakeup Interrupt Disable */
+#define CAN_IDR_TOVF (0x1u << 22) /**< \brief (CAN_IDR) Timer Overflow Interrupt */
+#define CAN_IDR_TSTP (0x1u << 23) /**< \brief (CAN_IDR) TimeStamp Interrupt Disable */
+#define CAN_IDR_CERR (0x1u << 24) /**< \brief (CAN_IDR) CRC Error Interrupt Disable */
+#define CAN_IDR_SERR (0x1u << 25) /**< \brief (CAN_IDR) Stuffing Error Interrupt Disable */
+#define CAN_IDR_AERR (0x1u << 26) /**< \brief (CAN_IDR) Acknowledgment Error Interrupt Disable */
+#define CAN_IDR_FERR (0x1u << 27) /**< \brief (CAN_IDR) Form Error Interrupt Disable */
+#define CAN_IDR_BERR (0x1u << 28) /**< \brief (CAN_IDR) Bit Error Interrupt Disable */
+/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */
+#define CAN_IMR_MB0 (0x1u << 0) /**< \brief (CAN_IMR) Mailbox 0 Interrupt Mask */
+#define CAN_IMR_MB1 (0x1u << 1) /**< \brief (CAN_IMR) Mailbox 1 Interrupt Mask */
+#define CAN_IMR_MB2 (0x1u << 2) /**< \brief (CAN_IMR) Mailbox 2 Interrupt Mask */
+#define CAN_IMR_MB3 (0x1u << 3) /**< \brief (CAN_IMR) Mailbox 3 Interrupt Mask */
+#define CAN_IMR_MB4 (0x1u << 4) /**< \brief (CAN_IMR) Mailbox 4 Interrupt Mask */
+#define CAN_IMR_MB5 (0x1u << 5) /**< \brief (CAN_IMR) Mailbox 5 Interrupt Mask */
+#define CAN_IMR_MB6 (0x1u << 6) /**< \brief (CAN_IMR) Mailbox 6 Interrupt Mask */
+#define CAN_IMR_MB7 (0x1u << 7) /**< \brief (CAN_IMR) Mailbox 7 Interrupt Mask */
+#define CAN_IMR_ERRA (0x1u << 16) /**< \brief (CAN_IMR) Error Active Mode Interrupt Mask */
+#define CAN_IMR_WARN (0x1u << 17) /**< \brief (CAN_IMR) Warning Limit Interrupt Mask */
+#define CAN_IMR_ERRP (0x1u << 18) /**< \brief (CAN_IMR) Error Passive Mode Interrupt Mask */
+#define CAN_IMR_BOFF (0x1u << 19) /**< \brief (CAN_IMR) Bus Off Mode Interrupt Mask */
+#define CAN_IMR_SLEEP (0x1u << 20) /**< \brief (CAN_IMR) Sleep Interrupt Mask */
+#define CAN_IMR_WAKEUP (0x1u << 21) /**< \brief (CAN_IMR) Wakeup Interrupt Mask */
+#define CAN_IMR_TOVF (0x1u << 22) /**< \brief (CAN_IMR) Timer Overflow Interrupt Mask */
+#define CAN_IMR_TSTP (0x1u << 23) /**< \brief (CAN_IMR) Timestamp Interrupt Mask */
+#define CAN_IMR_CERR (0x1u << 24) /**< \brief (CAN_IMR) CRC Error Interrupt Mask */
+#define CAN_IMR_SERR (0x1u << 25) /**< \brief (CAN_IMR) Stuffing Error Interrupt Mask */
+#define CAN_IMR_AERR (0x1u << 26) /**< \brief (CAN_IMR) Acknowledgment Error Interrupt Mask */
+#define CAN_IMR_FERR (0x1u << 27) /**< \brief (CAN_IMR) Form Error Interrupt Mask */
+#define CAN_IMR_BERR (0x1u << 28) /**< \brief (CAN_IMR) Bit Error Interrupt Mask */
+/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */
+#define CAN_SR_MB0 (0x1u << 0) /**< \brief (CAN_SR) Mailbox 0 Event */
+#define CAN_SR_MB1 (0x1u << 1) /**< \brief (CAN_SR) Mailbox 1 Event */
+#define CAN_SR_MB2 (0x1u << 2) /**< \brief (CAN_SR) Mailbox 2 Event */
+#define CAN_SR_MB3 (0x1u << 3) /**< \brief (CAN_SR) Mailbox 3 Event */
+#define CAN_SR_MB4 (0x1u << 4) /**< \brief (CAN_SR) Mailbox 4 Event */
+#define CAN_SR_MB5 (0x1u << 5) /**< \brief (CAN_SR) Mailbox 5 Event */
+#define CAN_SR_MB6 (0x1u << 6) /**< \brief (CAN_SR) Mailbox 6 Event */
+#define CAN_SR_MB7 (0x1u << 7) /**< \brief (CAN_SR) Mailbox 7 Event */
+#define CAN_SR_ERRA (0x1u << 16) /**< \brief (CAN_SR) Error Active Mode */
+#define CAN_SR_WARN (0x1u << 17) /**< \brief (CAN_SR) Warning Limit */
+#define CAN_SR_ERRP (0x1u << 18) /**< \brief (CAN_SR) Error Passive Mode */
+#define CAN_SR_BOFF (0x1u << 19) /**< \brief (CAN_SR) Bus Off Mode */
+#define CAN_SR_SLEEP (0x1u << 20) /**< \brief (CAN_SR) CAN controller in Low power Mode */
+#define CAN_SR_WAKEUP (0x1u << 21) /**< \brief (CAN_SR) CAN controller is not in Low power Mode */
+#define CAN_SR_TOVF (0x1u << 22) /**< \brief (CAN_SR) Timer Overflow */
+#define CAN_SR_TSTP (0x1u << 23) /**< \brief (CAN_SR)  */
+#define CAN_SR_CERR (0x1u << 24) /**< \brief (CAN_SR) Mailbox CRC Error */
+#define CAN_SR_SERR (0x1u << 25) /**< \brief (CAN_SR) Mailbox Stuffing Error */
+#define CAN_SR_AERR (0x1u << 26) /**< \brief (CAN_SR) Acknowledgment Error */
+#define CAN_SR_FERR (0x1u << 27) /**< \brief (CAN_SR) Form Error */
+#define CAN_SR_BERR (0x1u << 28) /**< \brief (CAN_SR) Bit Error */
+#define CAN_SR_RBSY (0x1u << 29) /**< \brief (CAN_SR) Receiver busy */
+#define CAN_SR_TBSY (0x1u << 30) /**< \brief (CAN_SR) Transmitter busy */
+#define CAN_SR_OVLSY (0x1u << 31) /**< \brief (CAN_SR) Overload busy */
+/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */
+#define CAN_BR_PHASE2_Pos 0
+#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) /**< \brief (CAN_BR) Phase 2 segment */
+#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos)))
+#define CAN_BR_PHASE1_Pos 4
+#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) /**< \brief (CAN_BR) Phase 1 segment */
+#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos)))
+#define CAN_BR_PROPAG_Pos 8
+#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) /**< \brief (CAN_BR) Programming time segment */
+#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos)))
+#define CAN_BR_SJW_Pos 12
+#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) /**< \brief (CAN_BR) Re-synchronization jump width */
+#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos)))
+#define CAN_BR_BRP_Pos 16
+#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) /**< \brief (CAN_BR) Baudrate Prescaler. */
+#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos)))
+#define CAN_BR_SMP (0x1u << 24) /**< \brief (CAN_BR) Sampling Mode */
+#define   CAN_BR_SMP_ONCE (0x0u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled once at sample point. */
+#define   CAN_BR_SMP_THREE (0x1u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. */
+/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */
+#define CAN_TIM_TIMER_Pos 0
+#define CAN_TIM_TIMER_Msk (0xffffu << CAN_TIM_TIMER_Pos) /**< \brief (CAN_TIM) Timer */
+/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */
+#define CAN_TIMESTP_MTIMESTAMP_Pos 0
+#define CAN_TIMESTP_MTIMESTAMP_Msk (0xffffu << CAN_TIMESTP_MTIMESTAMP_Pos) /**< \brief (CAN_TIMESTP) Timestamp */
+/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */
+#define CAN_ECR_REC_Pos 0
+#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) /**< \brief (CAN_ECR) Receive Error Counter */
+#define CAN_ECR_TEC_Pos 16
+#define CAN_ECR_TEC_Msk (0xffu << CAN_ECR_TEC_Pos) /**< \brief (CAN_ECR) Transmit Error Counter */
+/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */
+#define CAN_TCR_MB0 (0x1u << 0) /**< \brief (CAN_TCR) Transfer Request for Mailbox 0 */
+#define CAN_TCR_MB1 (0x1u << 1) /**< \brief (CAN_TCR) Transfer Request for Mailbox 1 */
+#define CAN_TCR_MB2 (0x1u << 2) /**< \brief (CAN_TCR) Transfer Request for Mailbox 2 */
+#define CAN_TCR_MB3 (0x1u << 3) /**< \brief (CAN_TCR) Transfer Request for Mailbox 3 */
+#define CAN_TCR_MB4 (0x1u << 4) /**< \brief (CAN_TCR) Transfer Request for Mailbox 4 */
+#define CAN_TCR_MB5 (0x1u << 5) /**< \brief (CAN_TCR) Transfer Request for Mailbox 5 */
+#define CAN_TCR_MB6 (0x1u << 6) /**< \brief (CAN_TCR) Transfer Request for Mailbox 6 */
+#define CAN_TCR_MB7 (0x1u << 7) /**< \brief (CAN_TCR) Transfer Request for Mailbox 7 */
+#define CAN_TCR_TIMRST (0x1u << 31) /**< \brief (CAN_TCR) Timer Reset */
+/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */
+#define CAN_ACR_MB0 (0x1u << 0) /**< \brief (CAN_ACR) Abort Request for Mailbox 0 */
+#define CAN_ACR_MB1 (0x1u << 1) /**< \brief (CAN_ACR) Abort Request for Mailbox 1 */
+#define CAN_ACR_MB2 (0x1u << 2) /**< \brief (CAN_ACR) Abort Request for Mailbox 2 */
+#define CAN_ACR_MB3 (0x1u << 3) /**< \brief (CAN_ACR) Abort Request for Mailbox 3 */
+#define CAN_ACR_MB4 (0x1u << 4) /**< \brief (CAN_ACR) Abort Request for Mailbox 4 */
+#define CAN_ACR_MB5 (0x1u << 5) /**< \brief (CAN_ACR) Abort Request for Mailbox 5 */
+#define CAN_ACR_MB6 (0x1u << 6) /**< \brief (CAN_ACR) Abort Request for Mailbox 6 */
+#define CAN_ACR_MB7 (0x1u << 7) /**< \brief (CAN_ACR) Abort Request for Mailbox 7 */
+/* -------- CAN_WPMR : (CAN Offset: 0x00E4) Write Protect Mode Register -------- */
+#define CAN_WPMR_WPEN (0x1u << 0) /**< \brief (CAN_WPMR) Write Protection Enable */
+#define CAN_WPMR_WPKEY_Pos 8
+#define CAN_WPMR_WPKEY_Msk (0xffffffu << CAN_WPMR_WPKEY_Pos) /**< \brief (CAN_WPMR) SPI Write Protection Key Password */
+#define CAN_WPMR_WPKEY(value) ((CAN_WPMR_WPKEY_Msk & ((value) << CAN_WPMR_WPKEY_Pos)))
+/* -------- CAN_WPSR : (CAN Offset: 0x00E8) Write Protect Status Register -------- */
+#define CAN_WPSR_WPVS (0x1u << 0) /**< \brief (CAN_WPSR) Write Protection Violation Status */
+#define CAN_WPSR_WPVSRC_Pos 8
+#define CAN_WPSR_WPVSRC_Msk (0xffu << CAN_WPSR_WPVSRC_Pos) /**< \brief (CAN_WPSR) Write Protection Violation Source */
+/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */
+#define CAN_MMR_MTIMEMARK_Pos 0
+#define CAN_MMR_MTIMEMARK_Msk (0xffffu << CAN_MMR_MTIMEMARK_Pos) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK(value) ((CAN_MMR_MTIMEMARK_Msk & ((value) << CAN_MMR_MTIMEMARK_Pos)))
+#define CAN_MMR_PRIOR_Pos 16
+#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) /**< \brief (CAN_MMR) Mailbox Priority */
+#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos)))
+#define CAN_MMR_MOT_Pos 24
+#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) /**< \brief (CAN_MMR) Mailbox Object Type */
+#define   CAN_MMR_MOT_MB_DISABLED (0x0u << 24) /**< \brief (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. */
+#define   CAN_MMR_MOT_MB_RX (0x1u << 24) /**< \brief (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. */
+#define   CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) /**< \brief (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. */
+#define   CAN_MMR_MOT_MB_TX (0x3u << 24) /**< \brief (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission. */
+#define   CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) /**< \brief (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. */
+#define   CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) /**< \brief (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. */
+/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */
+#define CAN_MAM_MIDvB_Pos 0
+#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) /**< \brief (CAN_MAM) Complementary bits for identifier in extended frame mode */
+#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos)))
+#define CAN_MAM_MIDvA_Pos 18
+#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) /**< \brief (CAN_MAM) Identifier for standard frame mode */
+#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos)))
+#define CAN_MAM_MIDE (0x1u << 29) /**< \brief (CAN_MAM) Identifier Version */
+/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */
+#define CAN_MID_MIDvB_Pos 0
+#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) /**< \brief (CAN_MID) Complementary bits for identifier in extended frame mode */
+#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos)))
+#define CAN_MID_MIDvA_Pos 18
+#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) /**< \brief (CAN_MID) Identifier for standard frame mode */
+#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos)))
+#define CAN_MID_MIDE (0x1u << 29) /**< \brief (CAN_MID) Identifier Version */
+/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */
+#define CAN_MFID_MFID_Pos 0
+#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) /**< \brief (CAN_MFID) Family ID */
+/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */
+#define CAN_MSR_MTIMESTAMP_Pos 0
+#define CAN_MSR_MTIMESTAMP_Msk (0xffffu << CAN_MSR_MTIMESTAMP_Pos) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MDLC_Pos 16
+#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) /**< \brief (CAN_MSR) Mailbox Data Length Code */
+#define CAN_MSR_MRTR (0x1u << 20) /**< \brief (CAN_MSR) Mailbox Remote Transmission Request */
+#define CAN_MSR_MABT (0x1u << 22) /**< \brief (CAN_MSR) Mailbox Message Abort */
+#define CAN_MSR_MRDY (0x1u << 23) /**< \brief (CAN_MSR) Mailbox Ready */
+#define CAN_MSR_MMI (0x1u << 24) /**< \brief (CAN_MSR) Mailbox Message Ignored */
+/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */
+#define CAN_MDL_MDL_Pos 0
+#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) /**< \brief (CAN_MDL) Message Data Low Value */
+#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos)))
+/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */
+#define CAN_MDH_MDH_Pos 0
+#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) /**< \brief (CAN_MDH) Message Data High Value */
+#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos)))
+/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */
+#define CAN_MCR_MDLC_Pos 16
+#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) /**< \brief (CAN_MCR) Mailbox Data Length Code */
+#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos)))
+#define CAN_MCR_MRTR (0x1u << 20) /**< \brief (CAN_MCR) Mailbox Remote Transmission Request */
+#define CAN_MCR_MACR (0x1u << 22) /**< \brief (CAN_MCR) Abort Request for Mailbox x */
+#define CAN_MCR_MTCR (0x1u << 23) /**< \brief (CAN_MCR) Mailbox Transfer Command */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_CAN_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_chipid.h

@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CHIPID_COMPONENT_
+#define _SAM3XA_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_CHIPID Chip Identifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_CHIPID_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_dacc.h

@@ -0,0 +1,210 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DACC_COMPONENT_
+#define _SAM3XA_DACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Dacc hardware registers */
+typedef struct {
+  WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
+  RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg DACC_CHER;     /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
+  WoReg DACC_CHDR;     /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
+  RoReg DACC_CHSR;     /**< \brief (Dacc Offset: 0x18) Channel Status Register */
+  RoReg Reserved2[1];
+  WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
+  WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
+  WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
+  RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
+  RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved3[24];
+  RwReg DACC_ACR;      /**< \brief (Dacc Offset: 0x94) Analog Current Register */
+  RoReg Reserved4[19];
+  RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
+  RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
+  RoReg Reserved5[7];
+  RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+  RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+  RoReg Reserved6[2];
+  RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+  RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define   DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */
+#define   DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define   DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */
+#define   DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
+#define DACC_MR_REFRESH_Pos 8
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
+#define DACC_MR_USER_SEL_Pos 16
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */
+#define   DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */
+#define   DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */
+#define   DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */
+#define   DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */
+#define   DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */
+#define   DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */
+#define DACC_MR_STARTUP_Pos 24
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define   DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */
+#define   DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */
+#define   DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */
+#define   DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */
+#define   DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */
+#define   DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */
+#define   DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */
+#define   DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */
+#define   DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */
+#define   DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */
+#define   DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */
+#define   DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */
+#define   DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */
+#define   DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */
+#define   DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */
+#define   DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */
+#define   DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */
+#define   DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */
+#define   DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */
+#define   DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */
+#define   DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */
+#define   DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */
+#define   DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */
+#define   DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */
+#define   DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */
+#define   DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */
+#define   DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */
+#define   DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */
+#define   DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */
+#define   DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */
+#define   DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */
+#define   DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
+#define DACC_ACR_IBCTLCH0_Pos 0
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
+#define DACC_ACR_IBCTLCH1_Pos 2
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
+#define DACC_ACR_IBCTLDACCORE_Pos 8
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_DACC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_dmac.h

@@ -0,0 +1,367 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DMAC_COMPONENT_
+#define _SAM3XA_DMAC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_DMAC DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief DmacCh_num hardware registers */
+typedef struct {
+  RwReg       DMAC_SADDR;     /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
+  RwReg       DMAC_DADDR;     /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
+  RwReg       DMAC_DSCR;      /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
+  RwReg       DMAC_CTRLA;     /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
+  RwReg       DMAC_CTRLB;     /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
+  RwReg       DMAC_CFG;       /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
+  RoReg       Reserved1[4];
+} DmacCh_num;
+/** \brief Dmac hardware registers */
+#define DMACCH_NUM_NUMBER 6
+typedef struct {
+  RwReg       DMAC_GCFG;      /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
+  RwReg       DMAC_EN;        /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
+  RwReg       DMAC_SREQ;      /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
+  RwReg       DMAC_CREQ;      /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
+  RwReg       DMAC_LAST;      /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
+  RoReg       Reserved1[1];
+  WoReg       DMAC_EBCIER;    /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+  WoReg       DMAC_EBCIDR;    /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+  RoReg       DMAC_EBCIMR;    /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+  RoReg       DMAC_EBCISR;    /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+  WoReg       DMAC_CHER;      /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
+  WoReg       DMAC_CHDR;      /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
+  RoReg       DMAC_CHSR;      /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
+  RoReg       Reserved2[2];
+  DmacCh_num  DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 5 */
+  RoReg       Reserved3[46];
+  RwReg       DMAC_WPMR;      /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */
+  RoReg       DMAC_WPSR;      /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
+#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */
+#define   DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */
+#define   DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */
+/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
+#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN)  */
+/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
+#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ4 (0x1u << 8) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ4 (0x1u << 9) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ5 (0x1u << 10) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ5 (0x1u << 11) /**< \brief (DMAC_SREQ) Destination Request */
+/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
+#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ4 (0x1u << 8) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ4 (0x1u << 9) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ5 (0x1u << 10) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ5 (0x1u << 11) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
+#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST4 (0x1u << 8) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST4 (0x1u << 9) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST5 (0x1u << 10) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST5 (0x1u << 11) /**< \brief (DMAC_LAST) Destination Last */
+/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */
+#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */
+#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */
+#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */
+#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
+#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA4 (0x1u << 4) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA5 (0x1u << 5) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP4 (0x1u << 28) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP5 (0x1u << 29) /**< \brief (DMAC_CHER) Keep on [5:0] */
+/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
+#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS4 (0x1u << 4) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS5 (0x1u << 5) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES4 (0x1u << 12) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES5 (0x1u << 13) /**< \brief (DMAC_CHDR) Resume [5:0] */
+/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
+#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA4 (0x1u << 4) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA5 (0x1u << 5) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT4 (0x1u << 20) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT5 (0x1u << 21) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL4 (0x1u << 28) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL5 (0x1u << 29) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
+#define DMAC_SADDR_SADDR_Pos 0
+#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */
+#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))
+/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
+#define DMAC_DADDR_DADDR_Pos 0
+#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */
+#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))
+/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
+#define DMAC_DSCR_DSCR_Pos 2
+#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */
+#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))
+/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
+#define DMAC_CTRLA_BTSIZE_Pos 0
+#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */
+#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
+#define DMAC_CTRLA_SCSIZE_Pos 16
+#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */
+#define   DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_DCSIZE_Pos 20
+#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */
+#define   DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_SRC_WIDTH_Pos 24
+#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */
+#define   DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define   DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define   DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DST_WIDTH_Pos 28
+#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */
+#define   DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define   DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define   DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA)  */
+/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
+#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */
+#define   DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */
+#define   DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */
+#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */
+#define   DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */
+#define   DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */
+#define DMAC_CTRLB_FC_Pos 21
+#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */
+#define   DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */
+#define DMAC_CTRLB_SRC_INCR_Pos 24
+#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */
+#define   DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */
+#define   DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */
+#define   DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */
+#define DMAC_CTRLB_DST_INCR_Pos 28
+#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */
+#define   DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */
+#define   DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */
+#define   DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */
+#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB)  */
+/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
+#define DMAC_CFG_SRC_PER_Pos 0
+#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */
+#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
+#define DMAC_CFG_DST_PER_Pos 4
+#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */
+#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
+#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */
+#define   DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define   DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */
+#define   DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define   DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */
+#define   DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */
+#define   DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */
+#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */
+#define   DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */
+#define   DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */
+#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */
+#define   DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */
+#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */
+#define   DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */
+#define   DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */
+#define DMAC_CFG_AHB_PROT_Pos 24
+#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */
+#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
+#define DMAC_CFG_FIFOCFG_Pos 28
+#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */
+#define   DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */
+#define   DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */
+#define   DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */
+/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */
+#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */
+#define DMAC_WPMR_WPKEY_Pos 8
+#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */
+#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))
+/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */
+#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */
+#define DMAC_WPSR_WPVSRC_Pos 8
+#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_DMAC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_efc.h

@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EFC_COMPONENT_
+#define _SAM3XA_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_EFC Embedded Flash Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_EFC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_emac.h

@@ -0,0 +1,335 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EMAC_COMPONENT_
+#define _SAM3XA_EMAC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_EMAC Ethernet MAC 10/100 */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief EmacSa hardware registers */
+typedef struct {
+  RwReg   EMAC_SAxB;    /**< \brief (EmacSa Offset: 0x0) Specific Address 1 Bottom Register */
+  RwReg   EMAC_SAxT;    /**< \brief (EmacSa Offset: 0x4) Specific Address 1 Top Register */
+} EmacSa;
+/** \brief Emac hardware registers */
+#define EMACSA_NUMBER 4
+typedef struct {
+  RwReg   EMAC_NCR;     /**< \brief (Emac Offset: 0x00) Network Control Register */
+  RwReg   EMAC_NCFGR;   /**< \brief (Emac Offset: 0x04) Network Configuration Register */
+  RoReg   EMAC_NSR;     /**< \brief (Emac Offset: 0x08) Network Status Register */
+  RoReg   Reserved1[2];
+  RwReg   EMAC_TSR;     /**< \brief (Emac Offset: 0x14) Transmit Status Register */
+  RwReg   EMAC_RBQP;    /**< \brief (Emac Offset: 0x18) Receive Buffer Queue Pointer Register */
+  RwReg   EMAC_TBQP;    /**< \brief (Emac Offset: 0x1C) Transmit Buffer Queue Pointer Register */
+  RwReg   EMAC_RSR;     /**< \brief (Emac Offset: 0x20) Receive Status Register */
+  RwReg   EMAC_ISR;     /**< \brief (Emac Offset: 0x24) Interrupt Status Register */
+  WoReg   EMAC_IER;     /**< \brief (Emac Offset: 0x28) Interrupt Enable Register */
+  WoReg   EMAC_IDR;     /**< \brief (Emac Offset: 0x2C) Interrupt Disable Register */
+  RoReg   EMAC_IMR;     /**< \brief (Emac Offset: 0x30) Interrupt Mask Register */
+  RwReg   EMAC_MAN;     /**< \brief (Emac Offset: 0x34) Phy Maintenance Register */
+  RwReg   EMAC_PTR;     /**< \brief (Emac Offset: 0x38) Pause Time Register */
+  RwReg   EMAC_PFR;     /**< \brief (Emac Offset: 0x3C) Pause Frames Received Register */
+  RwReg   EMAC_FTO;     /**< \brief (Emac Offset: 0x40) Frames Transmitted Ok Register */
+  RwReg   EMAC_SCF;     /**< \brief (Emac Offset: 0x44) Single Collision Frames Register */
+  RwReg   EMAC_MCF;     /**< \brief (Emac Offset: 0x48) Multiple Collision Frames Register */
+  RwReg   EMAC_FRO;     /**< \brief (Emac Offset: 0x4C) Frames Received Ok Register */
+  RwReg   EMAC_FCSE;    /**< \brief (Emac Offset: 0x50) Frame Check Sequence Errors Register */
+  RwReg   EMAC_ALE;     /**< \brief (Emac Offset: 0x54) Alignment Errors Register */
+  RwReg   EMAC_DTF;     /**< \brief (Emac Offset: 0x58) Deferred Transmission Frames Register */
+  RwReg   EMAC_LCOL;    /**< \brief (Emac Offset: 0x5C) Late Collisions Register */
+  RwReg   EMAC_ECOL;    /**< \brief (Emac Offset: 0x60) Excessive Collisions Register */
+  RwReg   EMAC_TUND;    /**< \brief (Emac Offset: 0x64) Transmit Underrun Errors Register */
+  RwReg   EMAC_CSE;     /**< \brief (Emac Offset: 0x68) Carrier Sense Errors Register */
+  RwReg   EMAC_RRE;     /**< \brief (Emac Offset: 0x6C) Receive Resource Errors Register */
+  RwReg   EMAC_ROV;     /**< \brief (Emac Offset: 0x70) Receive Overrun Errors Register */
+  RwReg   EMAC_RSE;     /**< \brief (Emac Offset: 0x74) Receive Symbol Errors Register */
+  RwReg   EMAC_ELE;     /**< \brief (Emac Offset: 0x78) Excessive Length Errors Register */
+  RwReg   EMAC_RJA;     /**< \brief (Emac Offset: 0x7C) Receive Jabbers Register */
+  RwReg   EMAC_USF;     /**< \brief (Emac Offset: 0x80) Undersize Frames Register */
+  RwReg   EMAC_STE;     /**< \brief (Emac Offset: 0x84) SQE Test Errors Register */
+  RwReg   EMAC_RLE;     /**< \brief (Emac Offset: 0x88) Received Length Field Mismatch Register */
+  RoReg   Reserved2[1];
+  RwReg   EMAC_HRB;     /**< \brief (Emac Offset: 0x90) Hash Register Bottom [31:0] Register */
+  RwReg   EMAC_HRT;     /**< \brief (Emac Offset: 0x94) Hash Register Top [63:32] Register */
+  EmacSa  EMAC_SA[EMACSA_NUMBER]; /**< \brief (Emac Offset: 0x98) sa = 1 .. 4 */
+  RwReg   EMAC_TID;     /**< \brief (Emac Offset: 0xB8) Type ID Checking Register */
+  RoReg   Reserved3[1];
+  RwReg   EMAC_USRIO;   /**< \brief (Emac Offset: 0xC0) User Input/Output Register */
+} Emac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EMAC_NCR : (EMAC Offset: 0x00) Network Control Register -------- */
+#define EMAC_NCR_LB (0x1u << 0) /**< \brief (EMAC_NCR) LoopBack */
+#define EMAC_NCR_LLB (0x1u << 1) /**< \brief (EMAC_NCR) Loopback local */
+#define EMAC_NCR_RE (0x1u << 2) /**< \brief (EMAC_NCR) Receive enable */
+#define EMAC_NCR_TE (0x1u << 3) /**< \brief (EMAC_NCR) Transmit enable */
+#define EMAC_NCR_MPE (0x1u << 4) /**< \brief (EMAC_NCR) Management port enable */
+#define EMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (EMAC_NCR) Clear statistics registers */
+#define EMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (EMAC_NCR) Increment statistics registers */
+#define EMAC_NCR_WESTAT (0x1u << 7) /**< \brief (EMAC_NCR) Write enable for statistics registers */
+#define EMAC_NCR_BP (0x1u << 8) /**< \brief (EMAC_NCR) Back pressure */
+#define EMAC_NCR_TSTART (0x1u << 9) /**< \brief (EMAC_NCR) Start transmission */
+#define EMAC_NCR_THALT (0x1u << 10) /**< \brief (EMAC_NCR) Transmit halt */
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x04) Network Configuration Register -------- */
+#define EMAC_NCFGR_SPD (0x1u << 0) /**< \brief (EMAC_NCFGR) Speed */
+#define EMAC_NCFGR_FD (0x1u << 1) /**< \brief (EMAC_NCFGR) Full Duplex */
+#define EMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (EMAC_NCFGR) Jumbo Frames */
+#define EMAC_NCFGR_CAF (0x1u << 4) /**< \brief (EMAC_NCFGR) Copy All Frames */
+#define EMAC_NCFGR_NBC (0x1u << 5) /**< \brief (EMAC_NCFGR) No Broadcast */
+#define EMAC_NCFGR_MTI (0x1u << 6) /**< \brief (EMAC_NCFGR) Multicast Hash Enable */
+#define EMAC_NCFGR_UNI (0x1u << 7) /**< \brief (EMAC_NCFGR) Unicast Hash Enable */
+#define EMAC_NCFGR_BIG (0x1u << 8) /**< \brief (EMAC_NCFGR) Receive 1536 bytes frames */
+#define EMAC_NCFGR_CLK_Pos 10
+#define EMAC_NCFGR_CLK_Msk (0x3u << EMAC_NCFGR_CLK_Pos) /**< \brief (EMAC_NCFGR) MDC clock divider */
+#define   EMAC_NCFGR_CLK_MCK_8 (0x0u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz). */
+#define   EMAC_NCFGR_CLK_MCK_16 (0x1u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz). */
+#define   EMAC_NCFGR_CLK_MCK_32 (0x2u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz). */
+#define   EMAC_NCFGR_CLK_MCK_64 (0x3u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz). */
+#define EMAC_NCFGR_RTY (0x1u << 12) /**< \brief (EMAC_NCFGR) Retry test */
+#define EMAC_NCFGR_PAE (0x1u << 13) /**< \brief (EMAC_NCFGR) Pause Enable */
+#define EMAC_NCFGR_RBOF_Pos 14
+#define EMAC_NCFGR_RBOF_Msk (0x3u << EMAC_NCFGR_RBOF_Pos) /**< \brief (EMAC_NCFGR) Receive Buffer Offset */
+#define   EMAC_NCFGR_RBOF_OFFSET_0 (0x0u << 14) /**< \brief (EMAC_NCFGR) No offset from start of receive buffer. */
+#define   EMAC_NCFGR_RBOF_OFFSET_1 (0x1u << 14) /**< \brief (EMAC_NCFGR) One-byte offset from start of receive buffer. */
+#define   EMAC_NCFGR_RBOF_OFFSET_2 (0x2u << 14) /**< \brief (EMAC_NCFGR) Two-byte offset from start of receive buffer. */
+#define   EMAC_NCFGR_RBOF_OFFSET_3 (0x3u << 14) /**< \brief (EMAC_NCFGR) Three-byte offset from start of receive buffer. */
+#define EMAC_NCFGR_RLCE (0x1u << 16) /**< \brief (EMAC_NCFGR) Receive Length field Checking Enable */
+#define EMAC_NCFGR_DRFCS (0x1u << 17) /**< \brief (EMAC_NCFGR) Discard Receive FCS */
+#define EMAC_NCFGR_EFRHD (0x1u << 18) /**< \brief (EMAC_NCFGR)  */
+#define EMAC_NCFGR_IRXFCS (0x1u << 19) /**< \brief (EMAC_NCFGR) Ignore RX FCS */
+/* -------- EMAC_NSR : (EMAC Offset: 0x08) Network Status Register -------- */
+#define EMAC_NSR_MDIO (0x1u << 1) /**< \brief (EMAC_NSR)  */
+#define EMAC_NSR_IDLE (0x1u << 2) /**< \brief (EMAC_NSR)  */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+#define EMAC_TSR_UBR (0x1u << 0) /**< \brief (EMAC_TSR) Used Bit Read */
+#define EMAC_TSR_COL (0x1u << 1) /**< \brief (EMAC_TSR) Collision Occurred */
+#define EMAC_TSR_RLES (0x1u << 2) /**< \brief (EMAC_TSR) Retry Limit exceeded */
+#define EMAC_TSR_TGO (0x1u << 3) /**< \brief (EMAC_TSR) Transmit Go */
+#define EMAC_TSR_BEX (0x1u << 4) /**< \brief (EMAC_TSR) Buffers exhausted mid frame */
+#define EMAC_TSR_COMP (0x1u << 5) /**< \brief (EMAC_TSR) Transmit Complete */
+#define EMAC_TSR_UND (0x1u << 6) /**< \brief (EMAC_TSR) Transmit Underrun */
+/* -------- EMAC_RBQP : (EMAC Offset: 0x18) Receive Buffer Queue Pointer Register -------- */
+#define EMAC_RBQP_ADDR_Pos 2
+#define EMAC_RBQP_ADDR_Msk (0x3fffffffu << EMAC_RBQP_ADDR_Pos) /**< \brief (EMAC_RBQP) Receive buffer queue pointer address */
+#define EMAC_RBQP_ADDR(value) ((EMAC_RBQP_ADDR_Msk & ((value) << EMAC_RBQP_ADDR_Pos)))
+/* -------- EMAC_TBQP : (EMAC Offset: 0x1C) Transmit Buffer Queue Pointer Register -------- */
+#define EMAC_TBQP_ADDR_Pos 2
+#define EMAC_TBQP_ADDR_Msk (0x3fffffffu << EMAC_TBQP_ADDR_Pos) /**< \brief (EMAC_TBQP) Transmit buffer queue pointer address */
+#define EMAC_TBQP_ADDR(value) ((EMAC_TBQP_ADDR_Msk & ((value) << EMAC_TBQP_ADDR_Pos)))
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define EMAC_RSR_BNA (0x1u << 0) /**< \brief (EMAC_RSR) Buffer Not Available */
+#define EMAC_RSR_REC (0x1u << 1) /**< \brief (EMAC_RSR) Frame Received */
+#define EMAC_RSR_OVR (0x1u << 2) /**< \brief (EMAC_RSR) Receive Overrun */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define EMAC_ISR_MFD (0x1u << 0) /**< \brief (EMAC_ISR) Management Frame Done */
+#define EMAC_ISR_RCOMP (0x1u << 1) /**< \brief (EMAC_ISR) Receive Complete */
+#define EMAC_ISR_RXUBR (0x1u << 2) /**< \brief (EMAC_ISR) Receive Used Bit Read */
+#define EMAC_ISR_TXUBR (0x1u << 3) /**< \brief (EMAC_ISR) Transmit Used Bit Read */
+#define EMAC_ISR_TUND (0x1u << 4) /**< \brief (EMAC_ISR) Ethernet Transmit Buffer Underrun */
+#define EMAC_ISR_RLEX (0x1u << 5) /**< \brief (EMAC_ISR) Retry Limit Exceeded */
+#define EMAC_ISR_TXERR (0x1u << 6) /**< \brief (EMAC_ISR) Transmit Error */
+#define EMAC_ISR_TCOMP (0x1u << 7) /**< \brief (EMAC_ISR) Transmit Complete */
+#define EMAC_ISR_ROVR (0x1u << 10) /**< \brief (EMAC_ISR) Receive Overrun */
+#define EMAC_ISR_HRESP (0x1u << 11) /**< \brief (EMAC_ISR) Hresp not OK */
+#define EMAC_ISR_PFRE (0x1u << 12) /**< \brief (EMAC_ISR) Pause Frame Received */
+#define EMAC_ISR_PTZ (0x1u << 13) /**< \brief (EMAC_ISR) Pause Time Zero */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+#define EMAC_IER_MFD (0x1u << 0) /**< \brief (EMAC_IER) Management Frame sent */
+#define EMAC_IER_RCOMP (0x1u << 1) /**< \brief (EMAC_IER) Receive Complete */
+#define EMAC_IER_RXUBR (0x1u << 2) /**< \brief (EMAC_IER) Receive Used Bit Read */
+#define EMAC_IER_TXUBR (0x1u << 3) /**< \brief (EMAC_IER) Transmit Used Bit Read */
+#define EMAC_IER_TUND (0x1u << 4) /**< \brief (EMAC_IER) Ethernet Transmit Buffer Underrun */
+#define EMAC_IER_RLE (0x1u << 5) /**< \brief (EMAC_IER) Retry Limit Exceeded */
+#define EMAC_IER_TXERR (0x1u << 6) /**< \brief (EMAC_IER)  */
+#define EMAC_IER_TCOMP (0x1u << 7) /**< \brief (EMAC_IER) Transmit Complete */
+#define EMAC_IER_ROVR (0x1u << 10) /**< \brief (EMAC_IER) Receive Overrun */
+#define EMAC_IER_HRESP (0x1u << 11) /**< \brief (EMAC_IER) Hresp not OK */
+#define EMAC_IER_PFR (0x1u << 12) /**< \brief (EMAC_IER) Pause Frame Received */
+#define EMAC_IER_PTZ (0x1u << 13) /**< \brief (EMAC_IER) Pause Time Zero */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2C) Interrupt Disable Register -------- */
+#define EMAC_IDR_MFD (0x1u << 0) /**< \brief (EMAC_IDR) Management Frame sent */
+#define EMAC_IDR_RCOMP (0x1u << 1) /**< \brief (EMAC_IDR) Receive Complete */
+#define EMAC_IDR_RXUBR (0x1u << 2) /**< \brief (EMAC_IDR) Receive Used Bit Read */
+#define EMAC_IDR_TXUBR (0x1u << 3) /**< \brief (EMAC_IDR) Transmit Used Bit Read */
+#define EMAC_IDR_TUND (0x1u << 4) /**< \brief (EMAC_IDR) Ethernet Transmit Buffer Underrun */
+#define EMAC_IDR_RLE (0x1u << 5) /**< \brief (EMAC_IDR) Retry Limit Exceeded */
+#define EMAC_IDR_TXERR (0x1u << 6) /**< \brief (EMAC_IDR)  */
+#define EMAC_IDR_TCOMP (0x1u << 7) /**< \brief (EMAC_IDR) Transmit Complete */
+#define EMAC_IDR_ROVR (0x1u << 10) /**< \brief (EMAC_IDR) Receive Overrun */
+#define EMAC_IDR_HRESP (0x1u << 11) /**< \brief (EMAC_IDR) Hresp not OK */
+#define EMAC_IDR_PFR (0x1u << 12) /**< \brief (EMAC_IDR) Pause Frame Received */
+#define EMAC_IDR_PTZ (0x1u << 13) /**< \brief (EMAC_IDR) Pause Time Zero */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+#define EMAC_IMR_MFD (0x1u << 0) /**< \brief (EMAC_IMR) Management Frame sent */
+#define EMAC_IMR_RCOMP (0x1u << 1) /**< \brief (EMAC_IMR) Receive Complete */
+#define EMAC_IMR_RXUBR (0x1u << 2) /**< \brief (EMAC_IMR) Receive Used Bit Read */
+#define EMAC_IMR_TXUBR (0x1u << 3) /**< \brief (EMAC_IMR) Transmit Used Bit Read */
+#define EMAC_IMR_TUND (0x1u << 4) /**< \brief (EMAC_IMR) Ethernet Transmit Buffer Underrun */
+#define EMAC_IMR_RLE (0x1u << 5) /**< \brief (EMAC_IMR) Retry Limit Exceeded */
+#define EMAC_IMR_TXERR (0x1u << 6) /**< \brief (EMAC_IMR)  */
+#define EMAC_IMR_TCOMP (0x1u << 7) /**< \brief (EMAC_IMR) Transmit Complete */
+#define EMAC_IMR_ROVR (0x1u << 10) /**< \brief (EMAC_IMR) Receive Overrun */
+#define EMAC_IMR_HRESP (0x1u << 11) /**< \brief (EMAC_IMR) Hresp not OK */
+#define EMAC_IMR_PFR (0x1u << 12) /**< \brief (EMAC_IMR) Pause Frame Received */
+#define EMAC_IMR_PTZ (0x1u << 13) /**< \brief (EMAC_IMR) Pause Time Zero */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) Phy Maintenance Register -------- */
+#define EMAC_MAN_DATA_Pos 0
+#define EMAC_MAN_DATA_Msk (0xffffu << EMAC_MAN_DATA_Pos) /**< \brief (EMAC_MAN)  */
+#define EMAC_MAN_DATA(value) ((EMAC_MAN_DATA_Msk & ((value) << EMAC_MAN_DATA_Pos)))
+#define EMAC_MAN_CODE_Pos 16
+#define EMAC_MAN_CODE_Msk (0x3u << EMAC_MAN_CODE_Pos) /**< \brief (EMAC_MAN)  */
+#define EMAC_MAN_CODE(value) ((EMAC_MAN_CODE_Msk & ((value) << EMAC_MAN_CODE_Pos)))
+#define EMAC_MAN_REGA_Pos 18
+#define EMAC_MAN_REGA_Msk (0x1fu << EMAC_MAN_REGA_Pos) /**< \brief (EMAC_MAN) Register Address */
+#define EMAC_MAN_REGA(value) ((EMAC_MAN_REGA_Msk & ((value) << EMAC_MAN_REGA_Pos)))
+#define EMAC_MAN_PHYA_Pos 23
+#define EMAC_MAN_PHYA_Msk (0x1fu << EMAC_MAN_PHYA_Pos) /**< \brief (EMAC_MAN) PHY Address */
+#define EMAC_MAN_PHYA(value) ((EMAC_MAN_PHYA_Msk & ((value) << EMAC_MAN_PHYA_Pos)))
+#define EMAC_MAN_RW_Pos 28
+#define EMAC_MAN_RW_Msk (0x3u << EMAC_MAN_RW_Pos) /**< \brief (EMAC_MAN) Read-write */
+#define EMAC_MAN_RW(value) ((EMAC_MAN_RW_Msk & ((value) << EMAC_MAN_RW_Pos)))
+#define EMAC_MAN_SOF_Pos 30
+#define EMAC_MAN_SOF_Msk (0x3u << EMAC_MAN_SOF_Pos) /**< \brief (EMAC_MAN) Start of frame */
+#define EMAC_MAN_SOF(value) ((EMAC_MAN_SOF_Msk & ((value) << EMAC_MAN_SOF_Pos)))
+/* -------- EMAC_PTR : (EMAC Offset: 0x38) Pause Time Register -------- */
+#define EMAC_PTR_PTIME_Pos 0
+#define EMAC_PTR_PTIME_Msk (0xffffu << EMAC_PTR_PTIME_Pos) /**< \brief (EMAC_PTR) Pause Time */
+#define EMAC_PTR_PTIME(value) ((EMAC_PTR_PTIME_Msk & ((value) << EMAC_PTR_PTIME_Pos)))
+/* -------- EMAC_PFR : (EMAC Offset: 0x3C) Pause Frames Received Register -------- */
+#define EMAC_PFR_FROK_Pos 0
+#define EMAC_PFR_FROK_Msk (0xffffu << EMAC_PFR_FROK_Pos) /**< \brief (EMAC_PFR) Pause Frames received OK */
+#define EMAC_PFR_FROK(value) ((EMAC_PFR_FROK_Msk & ((value) << EMAC_PFR_FROK_Pos)))
+/* -------- EMAC_FTO : (EMAC Offset: 0x40) Frames Transmitted Ok Register -------- */
+#define EMAC_FTO_FTOK_Pos 0
+#define EMAC_FTO_FTOK_Msk (0xffffffu << EMAC_FTO_FTOK_Pos) /**< \brief (EMAC_FTO) Frames Transmitted OK */
+#define EMAC_FTO_FTOK(value) ((EMAC_FTO_FTOK_Msk & ((value) << EMAC_FTO_FTOK_Pos)))
+/* -------- EMAC_SCF : (EMAC Offset: 0x44) Single Collision Frames Register -------- */
+#define EMAC_SCF_SCF_Pos 0
+#define EMAC_SCF_SCF_Msk (0xffffu << EMAC_SCF_SCF_Pos) /**< \brief (EMAC_SCF) Single Collision Frames */
+#define EMAC_SCF_SCF(value) ((EMAC_SCF_SCF_Msk & ((value) << EMAC_SCF_SCF_Pos)))
+/* -------- EMAC_MCF : (EMAC Offset: 0x48) Multiple Collision Frames Register -------- */
+#define EMAC_MCF_MCF_Pos 0
+#define EMAC_MCF_MCF_Msk (0xffffu << EMAC_MCF_MCF_Pos) /**< \brief (EMAC_MCF) Multicollision Frames */
+#define EMAC_MCF_MCF(value) ((EMAC_MCF_MCF_Msk & ((value) << EMAC_MCF_MCF_Pos)))
+/* -------- EMAC_FRO : (EMAC Offset: 0x4C) Frames Received Ok Register -------- */
+#define EMAC_FRO_FROK_Pos 0
+#define EMAC_FRO_FROK_Msk (0xffffffu << EMAC_FRO_FROK_Pos) /**< \brief (EMAC_FRO) Frames Received OK */
+#define EMAC_FRO_FROK(value) ((EMAC_FRO_FROK_Msk & ((value) << EMAC_FRO_FROK_Pos)))
+/* -------- EMAC_FCSE : (EMAC Offset: 0x50) Frame Check Sequence Errors Register -------- */
+#define EMAC_FCSE_FCSE_Pos 0
+#define EMAC_FCSE_FCSE_Msk (0xffu << EMAC_FCSE_FCSE_Pos) /**< \brief (EMAC_FCSE) Frame Check Sequence Errors */
+#define EMAC_FCSE_FCSE(value) ((EMAC_FCSE_FCSE_Msk & ((value) << EMAC_FCSE_FCSE_Pos)))
+/* -------- EMAC_ALE : (EMAC Offset: 0x54) Alignment Errors Register -------- */
+#define EMAC_ALE_ALE_Pos 0
+#define EMAC_ALE_ALE_Msk (0xffu << EMAC_ALE_ALE_Pos) /**< \brief (EMAC_ALE) Alignment Errors */
+#define EMAC_ALE_ALE(value) ((EMAC_ALE_ALE_Msk & ((value) << EMAC_ALE_ALE_Pos)))
+/* -------- EMAC_DTF : (EMAC Offset: 0x58) Deferred Transmission Frames Register -------- */
+#define EMAC_DTF_DTF_Pos 0
+#define EMAC_DTF_DTF_Msk (0xffffu << EMAC_DTF_DTF_Pos) /**< \brief (EMAC_DTF) Deferred Transmission Frames */
+#define EMAC_DTF_DTF(value) ((EMAC_DTF_DTF_Msk & ((value) << EMAC_DTF_DTF_Pos)))
+/* -------- EMAC_LCOL : (EMAC Offset: 0x5C) Late Collisions Register -------- */
+#define EMAC_LCOL_LCOL_Pos 0
+#define EMAC_LCOL_LCOL_Msk (0xffu << EMAC_LCOL_LCOL_Pos) /**< \brief (EMAC_LCOL) Late Collisions */
+#define EMAC_LCOL_LCOL(value) ((EMAC_LCOL_LCOL_Msk & ((value) << EMAC_LCOL_LCOL_Pos)))
+/* -------- EMAC_ECOL : (EMAC Offset: 0x60) Excessive Collisions Register -------- */
+#define EMAC_ECOL_EXCOL_Pos 0
+#define EMAC_ECOL_EXCOL_Msk (0xffu << EMAC_ECOL_EXCOL_Pos) /**< \brief (EMAC_ECOL) Excessive Collisions */
+#define EMAC_ECOL_EXCOL(value) ((EMAC_ECOL_EXCOL_Msk & ((value) << EMAC_ECOL_EXCOL_Pos)))
+/* -------- EMAC_TUND : (EMAC Offset: 0x64) Transmit Underrun Errors Register -------- */
+#define EMAC_TUND_TUND_Pos 0
+#define EMAC_TUND_TUND_Msk (0xffu << EMAC_TUND_TUND_Pos) /**< \brief (EMAC_TUND) Transmit Underruns */
+#define EMAC_TUND_TUND(value) ((EMAC_TUND_TUND_Msk & ((value) << EMAC_TUND_TUND_Pos)))
+/* -------- EMAC_CSE : (EMAC Offset: 0x68) Carrier Sense Errors Register -------- */
+#define EMAC_CSE_CSE_Pos 0
+#define EMAC_CSE_CSE_Msk (0xffu << EMAC_CSE_CSE_Pos) /**< \brief (EMAC_CSE) Carrier Sense Errors */
+#define EMAC_CSE_CSE(value) ((EMAC_CSE_CSE_Msk & ((value) << EMAC_CSE_CSE_Pos)))
+/* -------- EMAC_RRE : (EMAC Offset: 0x6C) Receive Resource Errors Register -------- */
+#define EMAC_RRE_RRE_Pos 0
+#define EMAC_RRE_RRE_Msk (0xffffu << EMAC_RRE_RRE_Pos) /**< \brief (EMAC_RRE) Receive Resource Errors */
+#define EMAC_RRE_RRE(value) ((EMAC_RRE_RRE_Msk & ((value) << EMAC_RRE_RRE_Pos)))
+/* -------- EMAC_ROV : (EMAC Offset: 0x70) Receive Overrun Errors Register -------- */
+#define EMAC_ROV_ROVR_Pos 0
+#define EMAC_ROV_ROVR_Msk (0xffu << EMAC_ROV_ROVR_Pos) /**< \brief (EMAC_ROV) Receive Overrun */
+#define EMAC_ROV_ROVR(value) ((EMAC_ROV_ROVR_Msk & ((value) << EMAC_ROV_ROVR_Pos)))
+/* -------- EMAC_RSE : (EMAC Offset: 0x74) Receive Symbol Errors Register -------- */
+#define EMAC_RSE_RSE_Pos 0
+#define EMAC_RSE_RSE_Msk (0xffu << EMAC_RSE_RSE_Pos) /**< \brief (EMAC_RSE) Receive Symbol Errors */
+#define EMAC_RSE_RSE(value) ((EMAC_RSE_RSE_Msk & ((value) << EMAC_RSE_RSE_Pos)))
+/* -------- EMAC_ELE : (EMAC Offset: 0x78) Excessive Length Errors Register -------- */
+#define EMAC_ELE_EXL_Pos 0
+#define EMAC_ELE_EXL_Msk (0xffu << EMAC_ELE_EXL_Pos) /**< \brief (EMAC_ELE) Excessive Length Errors */
+#define EMAC_ELE_EXL(value) ((EMAC_ELE_EXL_Msk & ((value) << EMAC_ELE_EXL_Pos)))
+/* -------- EMAC_RJA : (EMAC Offset: 0x7C) Receive Jabbers Register -------- */
+#define EMAC_RJA_RJB_Pos 0
+#define EMAC_RJA_RJB_Msk (0xffu << EMAC_RJA_RJB_Pos) /**< \brief (EMAC_RJA) Receive Jabbers */
+#define EMAC_RJA_RJB(value) ((EMAC_RJA_RJB_Msk & ((value) << EMAC_RJA_RJB_Pos)))
+/* -------- EMAC_USF : (EMAC Offset: 0x80) Undersize Frames Register -------- */
+#define EMAC_USF_USF_Pos 0
+#define EMAC_USF_USF_Msk (0xffu << EMAC_USF_USF_Pos) /**< \brief (EMAC_USF) Undersize frames */
+#define EMAC_USF_USF(value) ((EMAC_USF_USF_Msk & ((value) << EMAC_USF_USF_Pos)))
+/* -------- EMAC_STE : (EMAC Offset: 0x84) SQE Test Errors Register -------- */
+#define EMAC_STE_SQER_Pos 0
+#define EMAC_STE_SQER_Msk (0xffu << EMAC_STE_SQER_Pos) /**< \brief (EMAC_STE) SQE test errors */
+#define EMAC_STE_SQER(value) ((EMAC_STE_SQER_Msk & ((value) << EMAC_STE_SQER_Pos)))
+/* -------- EMAC_RLE : (EMAC Offset: 0x88) Received Length Field Mismatch Register -------- */
+#define EMAC_RLE_RLFM_Pos 0
+#define EMAC_RLE_RLFM_Msk (0xffu << EMAC_RLE_RLFM_Pos) /**< \brief (EMAC_RLE) Receive Length Field Mismatch */
+#define EMAC_RLE_RLFM(value) ((EMAC_RLE_RLFM_Msk & ((value) << EMAC_RLE_RLFM_Pos)))
+/* -------- EMAC_HRB : (EMAC Offset: 0x90) Hash Register Bottom [31:0] Register -------- */
+#define EMAC_HRB_ADDR_Pos 0
+#define EMAC_HRB_ADDR_Msk (0xffffffffu << EMAC_HRB_ADDR_Pos) /**< \brief (EMAC_HRB)  */
+#define EMAC_HRB_ADDR(value) ((EMAC_HRB_ADDR_Msk & ((value) << EMAC_HRB_ADDR_Pos)))
+/* -------- EMAC_HRT : (EMAC Offset: 0x94) Hash Register Top [63:32] Register -------- */
+#define EMAC_HRT_ADDR_Pos 0
+#define EMAC_HRT_ADDR_Msk (0xffffffffu << EMAC_HRT_ADDR_Pos) /**< \brief (EMAC_HRT)  */
+#define EMAC_HRT_ADDR(value) ((EMAC_HRT_ADDR_Msk & ((value) << EMAC_HRT_ADDR_Pos)))
+/* -------- EMAC_SAxB : (EMAC Offset: N/A) Specific Address 1 Bottom Register -------- */
+#define EMAC_SAxB_ADDR_Pos 0
+#define EMAC_SAxB_ADDR_Msk (0xffffffffu << EMAC_SAxB_ADDR_Pos) /**< \brief (EMAC_SAxB)  */
+#define EMAC_SAxB_ADDR(value) ((EMAC_SAxB_ADDR_Msk & ((value) << EMAC_SAxB_ADDR_Pos)))
+/* -------- EMAC_SAxT : (EMAC Offset: N/A) Specific Address 1 Top Register -------- */
+#define EMAC_SAxT_ADDR_Pos 0
+#define EMAC_SAxT_ADDR_Msk (0xffffu << EMAC_SAxT_ADDR_Pos) /**< \brief (EMAC_SAxT)  */
+#define EMAC_SAxT_ADDR(value) ((EMAC_SAxT_ADDR_Msk & ((value) << EMAC_SAxT_ADDR_Pos)))
+/* -------- EMAC_TID : (EMAC Offset: 0xB8) Type ID Checking Register -------- */
+#define EMAC_TID_TID_Pos 0
+#define EMAC_TID_TID_Msk (0xffffu << EMAC_TID_TID_Pos) /**< \brief (EMAC_TID) Type ID checking */
+#define EMAC_TID_TID(value) ((EMAC_TID_TID_Msk & ((value) << EMAC_TID_TID_Pos)))
+/* -------- EMAC_USRIO : (EMAC Offset: 0xC0) User Input/Output Register -------- */
+#define EMAC_USRIO_RMII (0x1u << 0) /**< \brief (EMAC_USRIO) Reduce MII */
+#define EMAC_USRIO_CLKEN (0x1u << 1) /**< \brief (EMAC_USRIO) Clock Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_EMAC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_gpbr.h

@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_GPBR_COMPONENT_
+#define _SAM3XA_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_GPBR General Purpose Backup Register */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_GPBR_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_hsmci.h

@@ -0,0 +1,341 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_HSMCI_COMPONENT_
+#define _SAM3XA_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Hsmci hardware registers */
+typedef struct {
+  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
+  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
+  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
+  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
+  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
+  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
+  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+  RoReg Reserved1[2];
+  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
+  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+  RwReg HSMCI_DMA;       /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
+  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+  RoReg Reserved2[35];
+  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[69];
+  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) SDCARD/SDIO Slot B selected */
+#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_SR)  */
+#define HSMCI_SR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_SR)  */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */
+#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IER)  */
+#define HSMCI_IER_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IER)  */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
+#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IDR)  */
+#define HSMCI_IDR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IDR)  */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
+#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IMR)  */
+#define HSMCI_IMR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IMR)  */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
+#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
+#define HSMCI_DMA_OFFSET_Pos 0
+#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */
+#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))
+#define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
+#define   HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
+#define   HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */
+#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
+#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
+#define HSMCI_FIFO_DATA_Pos 0
+#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
+#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_HSMCI_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_matrix.h

@@ -0,0 +1,285 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_MATRIX_COMPONENT_
+#define _SAM3XA_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[6]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[10];
+  RwReg MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[7];
+  RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RwReg MATRIX_PRAS4;   /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+  RoReg Reserved7[1];
+  RwReg MATRIX_PRAS5;   /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
+  RoReg Reserved8[1];
+  RwReg MATRIX_PRAS6;   /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
+  RoReg Reserved9[1];
+  RwReg MATRIX_PRAS7;   /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
+  RoReg Reserved10[1];
+  RwReg MATRIX_PRAS8;   /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
+  RoReg Reserved11[1];
+  RoReg Reserved12[14];
+  RwReg MATRIX_MRCR;    /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
+  RoReg Reserved13[4];
+  RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+  RoReg Reserved14[51];
+  RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MATRIX_MCFG[6] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[6]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[9]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+#define MATRIX_PRAS0_M5PR_Pos 20
+#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */
+#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+#define MATRIX_PRAS1_M5PR_Pos 20
+#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */
+#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+#define MATRIX_PRAS2_M5PR_Pos 20
+#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */
+#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+#define MATRIX_PRAS3_M5PR_Pos 20
+#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */
+#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+#define MATRIX_PRAS4_M5PR_Pos 20
+#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */
+#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))
+/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
+#define MATRIX_PRAS5_M0PR_Pos 0
+#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
+#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
+#define MATRIX_PRAS5_M1PR_Pos 4
+#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
+#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
+#define MATRIX_PRAS5_M2PR_Pos 8
+#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
+#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
+#define MATRIX_PRAS5_M3PR_Pos 12
+#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
+#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
+#define MATRIX_PRAS5_M4PR_Pos 16
+#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
+#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
+#define MATRIX_PRAS5_M5PR_Pos 20
+#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */
+#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))
+/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
+#define MATRIX_PRAS6_M0PR_Pos 0
+#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
+#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
+#define MATRIX_PRAS6_M1PR_Pos 4
+#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
+#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
+#define MATRIX_PRAS6_M2PR_Pos 8
+#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
+#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
+#define MATRIX_PRAS6_M3PR_Pos 12
+#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
+#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
+#define MATRIX_PRAS6_M4PR_Pos 16
+#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
+#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
+#define MATRIX_PRAS6_M5PR_Pos 20
+#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /**< \brief (MATRIX_PRAS6) Master 5 Priority */
+#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos)))
+/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
+#define MATRIX_PRAS7_M0PR_Pos 0
+#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
+#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
+#define MATRIX_PRAS7_M1PR_Pos 4
+#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
+#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
+#define MATRIX_PRAS7_M2PR_Pos 8
+#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
+#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
+#define MATRIX_PRAS7_M3PR_Pos 12
+#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
+#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
+#define MATRIX_PRAS7_M4PR_Pos 16
+#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
+#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
+#define MATRIX_PRAS7_M5PR_Pos 20
+#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /**< \brief (MATRIX_PRAS7) Master 5 Priority */
+#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos)))
+/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
+#define MATRIX_PRAS8_M0PR_Pos 0
+#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
+#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
+#define MATRIX_PRAS8_M1PR_Pos 4
+#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
+#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
+#define MATRIX_PRAS8_M2PR_Pos 8
+#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
+#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
+#define MATRIX_PRAS8_M3PR_Pos 12
+#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
+#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
+#define MATRIX_PRAS8_M4PR_Pos 16
+#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
+#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
+#define MATRIX_PRAS8_M5PR_Pos 20
+#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /**< \brief (MATRIX_PRAS8) Master 5 Priority */
+#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos)))
+/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
+#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */
+#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */
+#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */
+#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */
+#define MATRIX_MRCR_RCB4_Pos 4
+#define MATRIX_MRCR_RCB4_Msk (0x3u << MATRIX_MRCR_RCB4_Pos) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */
+#define MATRIX_MRCR_RCB4(value) ((MATRIX_MRCR_RCB4_Msk & ((value) << MATRIX_MRCR_RCB4_Pos)))
+#define MATRIX_MRCR_RCB5 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 5 */
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PC0 or ERASE Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_MATRIX_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_pdc.h

@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PDC_COMPONENT_
+#define _SAM3XA_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PDC Peripheral DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PDC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_pmc.h

@@ -0,0 +1,416 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PMC_COMPONENT_
+#define _SAM3XA_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PMC Power Management Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RwReg CKGR_UCKR;     /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RoReg Reserved2[1];
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved3[1];
+  RwReg PMC_USB;       /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+  RoReg Reserved4[1];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved5[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved6[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved7[5];
+  WoReg PMC_PCER1;     /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+  WoReg PMC_PCDR1;     /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+  RoReg PMC_PCSR1;     /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+  RwReg PMC_PCR;       /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */
+} Pmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB OTG Clock (48 MHz, USB_48M) for UTMI */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB OTG Clock (48 MHz, USB_48M) for UTMI */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB OTG Clock (48 MHz, USB_48M) Clock Status */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
+#define CKGR_UCKR_UPLLCOUNT_Pos 20
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define   PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR)  */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
+/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
+#define PMC_PCR_PID_Pos 0
+#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */
+#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
+#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */
+#define PMC_PCR_DIV_Pos 16
+#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */
+#define   PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */
+#define   PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */
+#define   PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */
+#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PMC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_pwm.h

@@ -0,0 +1,667 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PWM_COMPONENT_
+#define _SAM3XA_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 8
+typedef struct {
+  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+  RwReg      PWM_FPE1;      /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register 1 */
+  RwReg      PWM_FPE2;      /**< \brief (Pwm Offset: 0x70) PWM Fault Protection Enable Register 2 */
+  RoReg      Reserved2[2];
+  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  RoReg      Reserved3[11];
+  RwReg      PWM_SMMR;      /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+  RoReg      Reserved4[12];
+  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+  RoReg      Reserved5[7];
+  RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+  RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+  RoReg      Reserved6[2];
+  RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+  RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+  WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+  RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+  RoReg      Reserved7[2];
+  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  RoReg      Reserved8[20];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 7 */
+} Pwm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID4 (0x1u << 4) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID5 (0x1u << 5) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID6 (0x1u << 6) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID7 (0x1u << 7) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID4 (0x1u << 4) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID5 (0x1u << 5) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID6 (0x1u << 6) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID7 (0x1u << 7) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID4 (0x1u << 4) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID5 (0x1u << 5) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID6 (0x1u << 6) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID7 (0x1u << 7) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_CHID4 (0x1u << 4) /**< \brief (PWM_IER1) Counter Event on Channel 4 Interrupt Enable */
+#define PWM_IER1_CHID5 (0x1u << 5) /**< \brief (PWM_IER1) Counter Event on Channel 5 Interrupt Enable */
+#define PWM_IER1_CHID6 (0x1u << 6) /**< \brief (PWM_IER1) Counter Event on Channel 6 Interrupt Enable */
+#define PWM_IER1_CHID7 (0x1u << 7) /**< \brief (PWM_IER1) Counter Event on Channel 7 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID4 (0x1u << 20) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 4 Interrupt Enable */
+#define PWM_IER1_FCHID5 (0x1u << 21) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 5 Interrupt Enable */
+#define PWM_IER1_FCHID6 (0x1u << 22) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 6 Interrupt Enable */
+#define PWM_IER1_FCHID7 (0x1u << 23) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 7 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_CHID4 (0x1u << 4) /**< \brief (PWM_IDR1) Counter Event on Channel 4 Interrupt Disable */
+#define PWM_IDR1_CHID5 (0x1u << 5) /**< \brief (PWM_IDR1) Counter Event on Channel 5 Interrupt Disable */
+#define PWM_IDR1_CHID6 (0x1u << 6) /**< \brief (PWM_IDR1) Counter Event on Channel 6 Interrupt Disable */
+#define PWM_IDR1_CHID7 (0x1u << 7) /**< \brief (PWM_IDR1) Counter Event on Channel 7 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 4 Interrupt Disable */
+#define PWM_IDR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 5 Interrupt Disable */
+#define PWM_IDR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 6 Interrupt Disable */
+#define PWM_IDR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 7 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_CHID4 (0x1u << 4) /**< \brief (PWM_IMR1) Counter Event on Channel 4 Interrupt Mask */
+#define PWM_IMR1_CHID5 (0x1u << 5) /**< \brief (PWM_IMR1) Counter Event on Channel 5 Interrupt Mask */
+#define PWM_IMR1_CHID6 (0x1u << 6) /**< \brief (PWM_IMR1) Counter Event on Channel 6 Interrupt Mask */
+#define PWM_IMR1_CHID7 (0x1u << 7) /**< \brief (PWM_IMR1) Counter Event on Channel 7 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 4 Interrupt Mask */
+#define PWM_IMR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 5 Interrupt Mask */
+#define PWM_IMR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 6 Interrupt Mask */
+#define PWM_IMR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 7 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_CHID4 (0x1u << 4) /**< \brief (PWM_ISR1) Counter Event on Channel 4 */
+#define PWM_ISR1_CHID5 (0x1u << 5) /**< \brief (PWM_ISR1) Counter Event on Channel 5 */
+#define PWM_ISR1_CHID6 (0x1u << 6) /**< \brief (PWM_ISR1) Counter Event on Channel 6 */
+#define PWM_ISR1_CHID7 (0x1u << 7) /**< \brief (PWM_ISR1) Counter Event on Channel 7 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+#define PWM_ISR1_FCHID4 (0x1u << 20) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 4 */
+#define PWM_ISR1_FCHID5 (0x1u << 21) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 5 */
+#define PWM_ISR1_FCHID6 (0x1u << 22) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 6 */
+#define PWM_ISR1_FCHID7 (0x1u << 23) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 7 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_SYNC4 (0x1u << 4) /**< \brief (PWM_SCM) Synchronous Channel 4 */
+#define PWM_SCM_SYNC5 (0x1u << 5) /**< \brief (PWM_SCM) Synchronous Channel 5 */
+#define PWM_SCM_SYNC6 (0x1u << 6) /**< \brief (PWM_SCM) Synchronous Channel 6 */
+#define PWM_SCM_SYNC7 (0x1u << 7) /**< \brief (PWM_SCM) Synchronous Channel 7 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVH4 (0x1u << 4) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 4 */
+#define PWM_OOV_OOVH5 (0x1u << 5) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 5 */
+#define PWM_OOV_OOVH6 (0x1u << 6) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 6 */
+#define PWM_OOV_OOVH7 (0x1u << 7) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 7 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+#define PWM_OOV_OOVL4 (0x1u << 20) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 4 */
+#define PWM_OOV_OOVL5 (0x1u << 21) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 5 */
+#define PWM_OOV_OOVL6 (0x1u << 22) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 6 */
+#define PWM_OOV_OOVL7 (0x1u << 23) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 7 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSH4 (0x1u << 4) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 4 */
+#define PWM_OS_OSH5 (0x1u << 5) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 5 */
+#define PWM_OS_OSH6 (0x1u << 6) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 6 */
+#define PWM_OS_OSH7 (0x1u << 7) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 7 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+#define PWM_OS_OSL4 (0x1u << 20) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 4 */
+#define PWM_OS_OSL5 (0x1u << 21) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 5 */
+#define PWM_OS_OSL6 (0x1u << 22) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 6 */
+#define PWM_OS_OSL7 (0x1u << 23) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 7 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSH4 (0x1u << 4) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 4 */
+#define PWM_OSS_OSSH5 (0x1u << 5) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 5 */
+#define PWM_OSS_OSSH6 (0x1u << 6) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 6 */
+#define PWM_OSS_OSSH7 (0x1u << 7) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 7 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+#define PWM_OSS_OSSL4 (0x1u << 20) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 4 */
+#define PWM_OSS_OSSL5 (0x1u << 21) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 5 */
+#define PWM_OSS_OSSL6 (0x1u << 22) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 6 */
+#define PWM_OSS_OSSL7 (0x1u << 23) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 7 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCH4 (0x1u << 4) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 4 */
+#define PWM_OSC_OSCH5 (0x1u << 5) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 5 */
+#define PWM_OSC_OSCH6 (0x1u << 6) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 6 */
+#define PWM_OSC_OSCH7 (0x1u << 7) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 7 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+#define PWM_OSC_OSCL4 (0x1u << 20) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 4 */
+#define PWM_OSC_OSCL5 (0x1u << 21) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 5 */
+#define PWM_OSC_OSCL6 (0x1u << 22) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 6 */
+#define PWM_OSC_OSCL7 (0x1u << 23) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 7 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPH4 (0x1u << 4) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 4 */
+#define PWM_OSSUPD_OSSUPH5 (0x1u << 5) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 5 */
+#define PWM_OSSUPD_OSSUPH6 (0x1u << 6) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 6 */
+#define PWM_OSSUPD_OSSUPH7 (0x1u << 7) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 7 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL4 (0x1u << 20) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 4 */
+#define PWM_OSSUPD_OSSUPL5 (0x1u << 21) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 5 */
+#define PWM_OSSUPD_OSSUPL6 (0x1u << 22) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 6 */
+#define PWM_OSSUPD_OSSUPL7 (0x1u << 23) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 7 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPH4 (0x1u << 4) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 4 */
+#define PWM_OSCUPD_OSCUPH5 (0x1u << 5) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 5 */
+#define PWM_OSCUPD_OSCUPH6 (0x1u << 6) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 6 */
+#define PWM_OSCUPD_OSCUPH7 (0x1u << 7) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 7 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL4 (0x1u << 20) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 4 */
+#define PWM_OSCUPD_OSCUPL5 (0x1u << 21) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 5 */
+#define PWM_OSCUPD_OSCUPDL6 (0x1u << 22) /**< \brief (PWM_OSCUPD)  */
+#define PWM_OSCUPD_OSCUPL7 (0x1u << 23) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 7 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVH4 (0x1u << 4) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 4 */
+#define PWM_FPV_FPVH5 (0x1u << 5) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 5 */
+#define PWM_FPV_FPVH6 (0x1u << 6) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 6 */
+#define PWM_FPV_FPVH7 (0x1u << 7) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 7 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+#define PWM_FPV_FPVL4 (0x1u << 20) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 4 */
+#define PWM_FPV_FPVL5 (0x1u << 21) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 5 */
+#define PWM_FPV_FPVL6 (0x1u << 22) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 6 */
+#define PWM_FPV_FPVL7 (0x1u << 23) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 7 */
+/* -------- PWM_FPE1 : (PWM Offset: 0x6C) PWM Fault Protection Enable Register 1 -------- */
+#define PWM_FPE1_FPE0_Pos 0
+#define PWM_FPE1_FPE0_Msk (0xffu << PWM_FPE1_FPE0_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE0(value) ((PWM_FPE1_FPE0_Msk & ((value) << PWM_FPE1_FPE0_Pos)))
+#define PWM_FPE1_FPE1_Pos 8
+#define PWM_FPE1_FPE1_Msk (0xffu << PWM_FPE1_FPE1_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE1(value) ((PWM_FPE1_FPE1_Msk & ((value) << PWM_FPE1_FPE1_Pos)))
+#define PWM_FPE1_FPE2_Pos 16
+#define PWM_FPE1_FPE2_Msk (0xffu << PWM_FPE1_FPE2_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE2(value) ((PWM_FPE1_FPE2_Msk & ((value) << PWM_FPE1_FPE2_Pos)))
+#define PWM_FPE1_FPE3_Pos 24
+#define PWM_FPE1_FPE3_Msk (0xffu << PWM_FPE1_FPE3_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE3(value) ((PWM_FPE1_FPE3_Msk & ((value) << PWM_FPE1_FPE3_Pos)))
+/* -------- PWM_FPE2 : (PWM Offset: 0x70) PWM Fault Protection Enable Register 2 -------- */
+#define PWM_FPE2_FPE4_Pos 0
+#define PWM_FPE2_FPE4_Msk (0xffu << PWM_FPE2_FPE4_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE4(value) ((PWM_FPE2_FPE4_Msk & ((value) << PWM_FPE2_FPE4_Pos)))
+#define PWM_FPE2_FPE5_Pos 8
+#define PWM_FPE2_FPE5_Msk (0xffu << PWM_FPE2_FPE5_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE5(value) ((PWM_FPE2_FPE5_Msk & ((value) << PWM_FPE2_FPE5_Pos)))
+#define PWM_FPE2_FPE6_Pos 16
+#define PWM_FPE2_FPE6_Msk (0xffu << PWM_FPE2_FPE6_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE6(value) ((PWM_FPE2_FPE6_Msk & ((value) << PWM_FPE2_FPE6_Pos)))
+#define PWM_FPE2_FPE7_Pos 24
+#define PWM_FPE2_FPE7_Msk (0xffu << PWM_FPE2_FPE7_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE7(value) ((PWM_FPE2_FPE7_Msk & ((value) << PWM_FPE2_FPE7_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN2 (0x1u << 2) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN3 (0x1u << 3) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN2 (0x1u << 18) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN3 (0x1u << 19) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PWM_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_rstc.h

@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RSTC_COMPONENT_
+#define _SAM3XA_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RSTC Reset Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_RSTC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_rtc.h

@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTC_COMPONENT_
+#define _SAM3XA_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RTC Real-time Clock */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;        /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;        /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;      /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;      /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR;    /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR;    /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;        /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;      /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;       /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;       /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;       /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;       /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+  RoReg Reserved1[45];
+  RwReg RTC_WPMR;      /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR)  */
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_RTC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_rtt.h

@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTT_COMPONENT_
+#define _SAM3XA_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RTT Real-time Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_RTT_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_sdramc.h

@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SDRAMC_COMPONENT_
+#define _SAM3XA_SDRAMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR SDRAM Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SDRAMC SDRAM Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Sdramc hardware registers */
+typedef struct {
+  RwReg SDRAMC_MR;    /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */
+  RwReg SDRAMC_TR;    /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */
+  RwReg SDRAMC_CR;    /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */
+  RoReg Reserved1[1];
+  RwReg SDRAMC_LPR;   /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */
+  WoReg SDRAMC_IER;   /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */
+  WoReg SDRAMC_IDR;   /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */
+  RoReg SDRAMC_IMR;   /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */
+  RoReg SDRAMC_ISR;   /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */
+  RwReg SDRAMC_MDR;   /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */
+  RwReg SDRAMC_CR1;   /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */
+  RwReg SDRAMC_OCMS;  /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register 1 */
+} Sdramc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */
+#define SDRAMC_MR_MODE_Pos 0
+#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */
+#define   SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */
+#define   SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */
+/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */
+#define SDRAMC_TR_COUNT_Pos 0
+#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */
+#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))
+/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */
+#define SDRAMC_CR_NC_Pos 0
+#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */
+#define   SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */
+#define   SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */
+#define   SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */
+#define   SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */
+#define SDRAMC_CR_NR_Pos 2
+#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */
+#define   SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */
+#define   SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */
+#define   SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */
+#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */
+#define   SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */
+#define   SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */
+#define SDRAMC_CR_CAS_Pos 5
+#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */
+#define   SDRAMC_CR_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */
+#define   SDRAMC_CR_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */
+#define   SDRAMC_CR_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */
+#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */
+#define SDRAMC_CR_TWR_Pos 8
+#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */
+#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))
+#define SDRAMC_CR_TRC_TRFC_Pos 12
+#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */
+#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))
+#define SDRAMC_CR_TRP_Pos 16
+#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */
+#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))
+#define SDRAMC_CR_TRCD_Pos 20
+#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */
+#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))
+#define SDRAMC_CR_TRAS_Pos 24
+#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */
+#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))
+#define SDRAMC_CR_TXSR_Pos 28
+#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */
+#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))
+/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */
+#define SDRAMC_LPR_LPCB_Pos 0
+#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */
+#define   SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */
+#define   SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */
+#define   SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */
+#define   SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */
+#define SDRAMC_LPR_PASR_Pos 4
+#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */
+#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))
+#define SDRAMC_LPR_TCSR_Pos 8
+#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */
+#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))
+#define SDRAMC_LPR_DS_Pos 10
+#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */
+#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))
+#define SDRAMC_LPR_TIMEOUT_Pos 12
+#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to define when low-power mode is enable */
+#define   SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. */
+#define   SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */
+#define   SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */
+/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */
+#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */
+/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */
+#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */
+/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */
+#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */
+/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */
+#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status */
+/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */
+#define SDRAMC_MDR_MD_Pos 0
+#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */
+#define   SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */
+#define   SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */
+/* -------- SDRAMC_CR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */
+#define SDRAMC_CR1_NC_Pos 0
+#define SDRAMC_CR1_NC_Msk (0x3u << SDRAMC_CR1_NC_Pos) /**< \brief (SDRAMC_CR1) Number of Column Bits */
+#define   SDRAMC_CR1_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR1) 8 column bits */
+#define   SDRAMC_CR1_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR1) 9 column bits */
+#define   SDRAMC_CR1_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR1) 10 column bits */
+#define   SDRAMC_CR1_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR1) 11 column bits */
+#define SDRAMC_CR1_NR_Pos 2
+#define SDRAMC_CR1_NR_Msk (0x3u << SDRAMC_CR1_NR_Pos) /**< \brief (SDRAMC_CR1) Number of Row Bits */
+#define   SDRAMC_CR1_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR1) 11 row bits */
+#define   SDRAMC_CR1_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR1) 12 row bits */
+#define   SDRAMC_CR1_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR1) 13 row bits */
+#define SDRAMC_CR1_NB (0x1u << 4) /**< \brief (SDRAMC_CR1) Number of Banks */
+#define   SDRAMC_CR1_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR1) 2 banks */
+#define   SDRAMC_CR1_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR1) 4 banks */
+#define SDRAMC_CR1_CAS_Pos 5
+#define SDRAMC_CR1_CAS_Msk (0x3u << SDRAMC_CR1_CAS_Pos) /**< \brief (SDRAMC_CR1) CAS Latency */
+#define   SDRAMC_CR1_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR1) 1 cycle CAS latency */
+#define   SDRAMC_CR1_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR1) 2 cycle CAS latency */
+#define   SDRAMC_CR1_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR1) 3 cycle CAS latency */
+#define SDRAMC_CR1_DBW (0x1u << 7) /**< \brief (SDRAMC_CR1) Data Bus Width */
+#define SDRAMC_CR1_TWR_Pos 8
+#define SDRAMC_CR1_TWR_Msk (0xfu << SDRAMC_CR1_TWR_Pos) /**< \brief (SDRAMC_CR1) Write Recovery Delay */
+#define SDRAMC_CR1_TWR(value) ((SDRAMC_CR1_TWR_Msk & ((value) << SDRAMC_CR1_TWR_Pos)))
+#define SDRAMC_CR1_TRC_TRFC_Pos 12
+#define SDRAMC_CR1_TRC_TRFC_Msk (0xfu << SDRAMC_CR1_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR1) Row Cycle Delay and Row Refresh Cycle */
+#define SDRAMC_CR1_TRC_TRFC(value) ((SDRAMC_CR1_TRC_TRFC_Msk & ((value) << SDRAMC_CR1_TRC_TRFC_Pos)))
+#define SDRAMC_CR1_TRP_Pos 16
+#define SDRAMC_CR1_TRP_Msk (0xfu << SDRAMC_CR1_TRP_Pos) /**< \brief (SDRAMC_CR1) Row Precharge Delay */
+#define SDRAMC_CR1_TRP(value) ((SDRAMC_CR1_TRP_Msk & ((value) << SDRAMC_CR1_TRP_Pos)))
+#define SDRAMC_CR1_TRCD_Pos 20
+#define SDRAMC_CR1_TRCD_Msk (0xfu << SDRAMC_CR1_TRCD_Pos) /**< \brief (SDRAMC_CR1) Row to Column Delay */
+#define SDRAMC_CR1_TRCD(value) ((SDRAMC_CR1_TRCD_Msk & ((value) << SDRAMC_CR1_TRCD_Pos)))
+#define SDRAMC_CR1_TRAS_Pos 24
+#define SDRAMC_CR1_TRAS_Msk (0xfu << SDRAMC_CR1_TRAS_Pos) /**< \brief (SDRAMC_CR1) Active to Precharge Delay */
+#define SDRAMC_CR1_TRAS(value) ((SDRAMC_CR1_TRAS_Msk & ((value) << SDRAMC_CR1_TRAS_Pos)))
+#define SDRAMC_CR1_TXSR_Pos 28
+#define SDRAMC_CR1_TXSR_Msk (0xfu << SDRAMC_CR1_TXSR_Pos) /**< \brief (SDRAMC_CR1) Exit Self Refresh to Active Delay */
+#define SDRAMC_CR1_TXSR(value) ((SDRAMC_CR1_TXSR_Msk & ((value) << SDRAMC_CR1_TXSR_Pos)))
+/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register 1 -------- */
+#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SDRAMC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_smc.h

@@ -0,0 +1,484 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SMC_COMPONENT_
+#define _SAM3XA_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SMC Static Memory Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+  RwReg         SMC_TIMINGS;      /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */
+  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 8
+typedef struct {
+  RwReg         SMC_CFG;          /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
+  WoReg         SMC_CTRL;         /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
+  RoReg         SMC_SR;           /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
+  WoReg         SMC_IER;          /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
+  WoReg         SMC_IDR;          /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
+  RoReg         SMC_IMR;          /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
+  RwReg         SMC_ADDR;         /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
+  RwReg         SMC_BANK;         /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
+  WoReg         SMC_ECC_CTRL;     /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
+  RwReg         SMC_ECC_MD;       /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
+  RoReg         SMC_ECC_SR1;      /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
+  RoReg         SMC_ECC_PR0;      /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
+  RoReg         SMC_ECC_PR1;      /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
+  RoReg         SMC_ECC_SR2;      /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
+  RoReg         SMC_ECC_PR2;      /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
+  RoReg         SMC_ECC_PR3;      /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
+  RoReg         SMC_ECC_PR4;      /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
+  RoReg         SMC_ECC_PR5;      /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
+  RoReg         SMC_ECC_PR6;      /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
+  RoReg         SMC_ECC_PR7;      /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
+  RoReg         SMC_ECC_PR8;      /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
+  RoReg         SMC_ECC_PR9;      /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
+  RoReg         SMC_ECC_PR10;     /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
+  RoReg         SMC_ECC_PR11;     /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
+  RoReg         SMC_ECC_PR12;     /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
+  RoReg         SMC_ECC_PR13;     /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
+  RoReg         SMC_ECC_PR14;     /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
+  RoReg         SMC_ECC_PR15;     /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
+  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 7 */
+  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x110) SMC OCMS Register */
+  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */
+  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */
+  RoReg         Reserved1[50];
+  WoReg         SMC_WPCR;         /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */
+  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */
+} Smc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
+#define SMC_CFG_PAGESIZE_Pos 0
+#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG)  */
+#define   SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define   SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define   SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define   SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */
+#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */
+#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
+#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
+#define SMC_CFG_DTOCYC_Pos 16
+#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
+#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))
+#define SMC_CFG_DTOMUL_Pos 20
+#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */
+#define   SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */
+#define   SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */
+#define   SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */
+#define   SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */
+#define   SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */
+#define   SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */
+#define   SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */
+#define   SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */
+/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
+#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
+#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
+/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
+#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */
+#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
+#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
+#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
+#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
+#define SMC_SR_NFCSID_Pos 12
+#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
+#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
+#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */
+#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */
+#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */
+#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */
+#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */
+#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */
+/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
+#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
+#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
+#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
+#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
+#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
+#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
+#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
+#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
+#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */
+/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
+#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
+#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
+#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
+#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
+#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
+#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
+#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
+#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
+#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */
+/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
+#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
+#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
+#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
+#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
+#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
+#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
+#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
+#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
+#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */
+/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
+#define SMC_ADDR_ADDR_CYCLE0_Pos 0
+#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */
+#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))
+/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
+#define SMC_BANK_BANK_Pos 0
+#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */
+#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos)))
+/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
+#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
+#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
+/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
+#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0
+#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_ECC_MD_TYPCORREC_Pos 4
+#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */
+#define   SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes  (for 8 or 16-bit NAND Flash) */
+#define   SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+#define   SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
+#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
+#define SMC_ECC_SR1_ECCERR0_Pos 1
+#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */
+#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_ECCERR4_Pos 17
+#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_ECCERR5_Pos 21
+#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_ECCERR6_Pos 25
+#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+#define SMC_ECC_SR1_ECCERR7_Pos 29
+#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
+#define SMC_ECC_PR0_BITADDR_Pos 0
+#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */
+#define SMC_ECC_PR0_WORDADDR_Pos 4
+#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */
+#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_Pos 12
+#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
+#define SMC_ECC_PR1_NPARITY_Pos 0
+#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_BITADDR_Pos 0
+#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_WORDADDR_Pos 3
+#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
+#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_ECCERR8_Pos 1
+#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_ECCERR12_Pos 17
+#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_ECCERR13_Pos 21
+#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_ECCERR14_Pos 25
+#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */
+#define SMC_ECC_SR2_ECCERR15_Pos 29
+#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */
+/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */
+#define SMC_ECC_PR2_BITADDR_Pos 0
+#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_WORDADDR_Pos 3
+#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_Pos 12
+#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */
+#define SMC_ECC_PR3_BITADDR_Pos 0
+#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_WORDADDR_Pos 3
+#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_Pos 12
+#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */
+#define SMC_ECC_PR4_BITADDR_Pos 0
+#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_WORDADDR_Pos 3
+#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_Pos 12
+#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */
+#define SMC_ECC_PR5_BITADDR_Pos 0
+#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_WORDADDR_Pos 3
+#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_Pos 12
+#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */
+#define SMC_ECC_PR6_BITADDR_Pos 0
+#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_WORDADDR_Pos 3
+#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_Pos 12
+#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */
+#define SMC_ECC_PR7_BITADDR_Pos 0
+#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_WORDADDR_Pos 3
+#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_Pos 12
+#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */
+#define SMC_ECC_PR8_BITADDR_Pos 0
+#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_WORDADDR_Pos 3
+#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_NPARITY_Pos 12
+#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */
+/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */
+#define SMC_ECC_PR9_BITADDR_Pos 0
+#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_WORDADDR_Pos 3
+#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_NPARITY_Pos 12
+#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */
+/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */
+#define SMC_ECC_PR10_BITADDR_Pos 0
+#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_WORDADDR_Pos 3
+#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_NPARITY_Pos 12
+#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */
+/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */
+#define SMC_ECC_PR11_BITADDR_Pos 0
+#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_WORDADDR_Pos 3
+#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_NPARITY_Pos 12
+#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */
+/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */
+#define SMC_ECC_PR12_BITADDR_Pos 0
+#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_WORDADDR_Pos 3
+#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_NPARITY_Pos 12
+#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */
+/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */
+#define SMC_ECC_PR13_BITADDR_Pos 0
+#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_WORDADDR_Pos 3
+#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_NPARITY_Pos 12
+#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */
+/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */
+#define SMC_ECC_PR14_BITADDR_Pos 0
+#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_WORDADDR_Pos 3
+#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_NPARITY_Pos 12
+#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */
+/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */
+#define SMC_ECC_PR15_BITADDR_Pos 0
+#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_WORDADDR_Pos 3
+#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_NPARITY_Pos 12
+#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */
+#define SMC_TIMINGS_TCLR_Pos 0
+#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */
+#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))
+#define SMC_TIMINGS_TADL_Pos 4
+#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */
+#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))
+#define SMC_TIMINGS_TAR_Pos 8
+#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */
+#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))
+#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */
+#define SMC_TIMINGS_TRR_Pos 16
+#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */
+#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))
+#define SMC_TIMINGS_TWB_Pos 24
+#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */
+#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))
+#define SMC_TIMINGS_RBNSEL_Pos 28
+#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */
+#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))
+#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
+#define   SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */
+#define   SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
+#define   SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */
+#define   SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
+#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
+#define   SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define   SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */
+#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */
+#define SMC_WPCR_WP_KEY_Pos 8
+#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */
+#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */
+#define SMC_WPSR_WP_VS_Pos 0
+#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */
+#define SMC_WPSR_WP_VSRC_Pos 8
+#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SMC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_spi.h

@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SPI_COMPONENT_
+#define _SAM3XA_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SPI Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+} Spi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
+#define SPI_WPMR_WPKEY_Pos 8
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
+#define SPI_WPSR_WPVSRC_Pos 8
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SPI_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_ssc.h

@@ -0,0 +1,270 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SSC_COMPONENT_
+#define _SAM3XA_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SSC Synchronous Serial Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Ssc hardware registers */
+typedef struct {
+  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  RoReg Reserved1[2];
+  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  RoReg Reserved2[2];
+  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved3[37];
+  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+} Ssc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SSC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_supc.h

@@ -0,0 +1,312 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SUPC_COMPONENT_
+#define _SAM3XA_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SUPC Supply Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR)  */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */
+#define   SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */
+#define   SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_FWUPDBC_Pos 8
+#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */
+#define   SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
+#define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
+#define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
+#define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
+#define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
+#define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
+#define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
+#define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
+#define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
+#define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
+#define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
+#define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
+#define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
+#define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
+#define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
+#define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
+#define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */
+#define   SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */
+#define   SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */
+#define   SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SUPC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_tc.h

@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TC_COMPONENT_
+#define _SAM3XA_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TC Timer Counter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  RwReg      TC_FMR;        /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
+  RoReg      Reserved1[2];
+  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_TC_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_trng.h

@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TRNG_COMPONENT_
+#define _SAM3XA_TRNG_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR True Random Number Generator */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TRNG True Random Number Generator */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Trng hardware registers */
+typedef struct {
+  WoReg TRNG_CR;       /**< \brief (Trng Offset: 0x00) Control Register */
+  RoReg Reserved1[3];
+  WoReg TRNG_IER;      /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */
+  WoReg TRNG_IDR;      /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */
+  RoReg TRNG_IMR;      /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */
+  RoReg TRNG_ISR;      /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */
+  RoReg Reserved2[12];
+  RoReg TRNG_ODATA;    /**< \brief (Trng Offset: 0x50) Output Data Register */
+} Trng;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */
+#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */
+#define TRNG_CR_KEY_Pos 8
+#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */
+#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))
+/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */
+#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */
+/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */
+#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */
+/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */
+#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */
+/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */
+#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */
+/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */
+#define TRNG_ODATA_ODATA_Pos 0
+#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_TRNG_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_twi.h

@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TWI_COMPONENT_
+#define _SAM3XA_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TWI Two-wire Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_TWI_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_uart.h

@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_UART_COMPONENT_
+#define _SAM3XA_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_UART_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_uotghs.h

@@ -0,0 +1,938 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_UOTGHS_COMPONENT_
+#define _SAM3XA_UOTGHS_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB On-The-Go Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_UOTGHS USB On-The-Go Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief UotghsDevdma hardware registers */
+typedef struct {
+  RwReg         UOTGHS_DEVDMANXTDSC;   /**< \brief (UotghsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */
+  RwReg         UOTGHS_DEVDMAADDRESS;  /**< \brief (UotghsDevdma Offset: 0x4) Device DMA Channel Address Register */
+  RwReg         UOTGHS_DEVDMACONTROL;  /**< \brief (UotghsDevdma Offset: 0x8) Device DMA Channel Control Register */
+  RwReg         UOTGHS_DEVDMASTATUS;   /**< \brief (UotghsDevdma Offset: 0xC) Device DMA Channel Status Register */
+} UotghsDevdma;
+/** \brief UotghsHstdma hardware registers */
+typedef struct {
+  RwReg         UOTGHS_HSTDMANXTDSC;   /**< \brief (UotghsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */
+  RwReg         UOTGHS_HSTDMAADDRESS;  /**< \brief (UotghsHstdma Offset: 0x4) Host DMA Channel Address Register */
+  RwReg         UOTGHS_HSTDMACONTROL;  /**< \brief (UotghsHstdma Offset: 0x8) Host DMA Channel Control Register */
+  RwReg         UOTGHS_HSTDMASTATUS;   /**< \brief (UotghsHstdma Offset: 0xC) Host DMA Channel Status Register */
+} UotghsHstdma;
+/** \brief Uotghs hardware registers */
+#define UOTGHSDEVDMA_NUMBER 7
+#define UOTGHSHSTDMA_NUMBER 7
+typedef struct {
+  RwReg         UOTGHS_DEVCTRL;        /**< \brief (Uotghs Offset: 0x0000) Device General Control Register */
+  RoReg         UOTGHS_DEVISR;         /**< \brief (Uotghs Offset: 0x0004) Device Global Interrupt Status Register */
+  WoReg         UOTGHS_DEVICR;         /**< \brief (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register */
+  WoReg         UOTGHS_DEVIFR;         /**< \brief (Uotghs Offset: 0x000C) Device Global Interrupt Set Register */
+  RoReg         UOTGHS_DEVIMR;         /**< \brief (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register */
+  WoReg         UOTGHS_DEVIDR;         /**< \brief (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register */
+  WoReg         UOTGHS_DEVIER;         /**< \brief (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register */
+  RwReg         UOTGHS_DEVEPT;         /**< \brief (Uotghs Offset: 0x001C) Device Endpoint Register */
+  RoReg         UOTGHS_DEVFNUM;        /**< \brief (Uotghs Offset: 0x0020) Device Frame Number Register */
+  RoReg         Reserved1[55];
+  RwReg         UOTGHS_DEVEPTCFG[10];  /**< \brief (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */
+  RoReg         Reserved2[2];
+  RoReg         UOTGHS_DEVEPTISR[10];  /**< \brief (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) */
+  RoReg         Reserved3[2];
+  WoReg         UOTGHS_DEVEPTICR[10];  /**< \brief (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) */
+  RoReg         Reserved4[2];
+  WoReg         UOTGHS_DEVEPTIFR[10];  /**< \brief (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) */
+  RoReg         Reserved5[2];
+  RoReg         UOTGHS_DEVEPTIMR[10];  /**< \brief (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */
+  RoReg         Reserved6[2];
+  WoReg         UOTGHS_DEVEPTIER[10];  /**< \brief (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */
+  RoReg         Reserved7[2];
+  WoReg         UOTGHS_DEVEPTIDR[10];  /**< \brief (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) */
+  RoReg         Reserved8[50];
+  UotghsDevdma  UOTGHS_DEVDMA[UOTGHSDEVDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x310) n = 1 .. 7 */
+  RoReg         Reserved9[32];
+  RwReg         UOTGHS_HSTCTRL;        /**< \brief (Uotghs Offset: 0x0400) Host General Control Register */
+  RoReg         UOTGHS_HSTISR;         /**< \brief (Uotghs Offset: 0x0404) Host Global Interrupt Status Register */
+  WoReg         UOTGHS_HSTICR;         /**< \brief (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register */
+  WoReg         UOTGHS_HSTIFR;         /**< \brief (Uotghs Offset: 0x040C) Host Global Interrupt Set Register */
+  RoReg         UOTGHS_HSTIMR;         /**< \brief (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register */
+  WoReg         UOTGHS_HSTIDR;         /**< \brief (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register */
+  WoReg         UOTGHS_HSTIER;         /**< \brief (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register */
+  RwReg         UOTGHS_HSTPIP;         /**< \brief (Uotghs Offset: 0x0041C) Host Pipe Register */
+  RwReg         UOTGHS_HSTFNUM;        /**< \brief (Uotghs Offset: 0x0420) Host Frame Number Register */
+  RwReg         UOTGHS_HSTADDR1;       /**< \brief (Uotghs Offset: 0x0424) Host Address 1 Register */
+  RwReg         UOTGHS_HSTADDR2;       /**< \brief (Uotghs Offset: 0x0428) Host Address 2 Register */
+  RwReg         UOTGHS_HSTADDR3;       /**< \brief (Uotghs Offset: 0x042C) Host Address 3 Register */
+  RoReg         Reserved10[52];
+  RwReg         UOTGHS_HSTPIPCFG[10];  /**< \brief (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) */
+  RoReg         Reserved11[2];
+  RoReg         UOTGHS_HSTPIPISR[10];  /**< \brief (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) */
+  RoReg         Reserved12[2];
+  WoReg         UOTGHS_HSTPIPICR[10];  /**< \brief (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) */
+  RoReg         Reserved13[2];
+  WoReg         UOTGHS_HSTPIPIFR[10];  /**< \brief (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) */
+  RoReg         Reserved14[2];
+  RoReg         UOTGHS_HSTPIPIMR[10];  /**< \brief (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */
+  RoReg         Reserved15[2];
+  WoReg         UOTGHS_HSTPIPIER[10];  /**< \brief (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */
+  RoReg         Reserved16[2];
+  WoReg         UOTGHS_HSTPIPIDR[10];  /**< \brief (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) */
+  RoReg         Reserved17[2];
+  RwReg         UOTGHS_HSTPIPINRQ[10]; /**< \brief (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) */
+  RoReg         Reserved18[2];
+  RwReg         UOTGHS_HSTPIPERR[10];  /**< \brief (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) */
+  RoReg         Reserved19[26];
+  UotghsHstdma  UOTGHS_HSTDMA[UOTGHSHSTDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x710) n = 1 .. 7 */
+  RoReg         Reserved20[32];
+  RwReg         UOTGHS_CTRL;           /**< \brief (Uotghs Offset: 0x0800) General Control Register */
+  RoReg         UOTGHS_SR;             /**< \brief (Uotghs Offset: 0x0804) General Status Register */
+  WoReg         UOTGHS_SCR;            /**< \brief (Uotghs Offset: 0x0808) General Status Clear Register */
+  WoReg         UOTGHS_SFR;            /**< \brief (Uotghs Offset: 0x080C) General Status Set Register */
+  RoReg         Reserved21[7];
+  RoReg         UOTGHS_FSM;            /**< \brief (Uotghs Offset: 0x082C) General Finite State Machine Register */
+} Uotghs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UOTGHS_DEVCTRL : (UOTGHS Offset: 0x0000) Device General Control Register -------- */
+#define UOTGHS_DEVCTRL_UADD_Pos 0
+#define UOTGHS_DEVCTRL_UADD_Msk (0x7fu << UOTGHS_DEVCTRL_UADD_Pos) /**< \brief (UOTGHS_DEVCTRL) USB Address */
+#define UOTGHS_DEVCTRL_UADD(value) ((UOTGHS_DEVCTRL_UADD_Msk & ((value) << UOTGHS_DEVCTRL_UADD_Pos)))
+#define UOTGHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (UOTGHS_DEVCTRL) Address Enable */
+#define UOTGHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (UOTGHS_DEVCTRL) Detach */
+#define UOTGHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (UOTGHS_DEVCTRL) Remote Wake-Up */
+#define UOTGHS_DEVCTRL_SPDCONF_Pos 10
+#define UOTGHS_DEVCTRL_SPDCONF_Msk (0x3u << UOTGHS_DEVCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_DEVCTRL) Mode Configuration */
+#define   UOTGHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. */
+#define   UOTGHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (UOTGHS_DEVCTRL) For a better consumption, if high-speed is not needed. */
+#define   UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (UOTGHS_DEVCTRL) Forced high speed. */
+#define   UOTGHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral remains in full-speed mode whatever the host speed capability. */
+#define UOTGHS_DEVCTRL_LS (0x1u << 12) /**< \brief (UOTGHS_DEVCTRL) Low-Speed Mode Force */
+#define UOTGHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (UOTGHS_DEVCTRL) Test mode J */
+#define UOTGHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (UOTGHS_DEVCTRL) Test mode K */
+#define UOTGHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (UOTGHS_DEVCTRL) Test packet mode */
+#define UOTGHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (UOTGHS_DEVCTRL) Specific Operational mode */
+/* -------- UOTGHS_DEVISR : (UOTGHS Offset: 0x0004) Device Global Interrupt Status Register -------- */
+#define UOTGHS_DEVISR_SUSP (0x1u << 0) /**< \brief (UOTGHS_DEVISR) Suspend Interrupt */
+#define UOTGHS_DEVISR_MSOF (0x1u << 1) /**< \brief (UOTGHS_DEVISR) Micro Start of Frame Interrupt */
+#define UOTGHS_DEVISR_SOF (0x1u << 2) /**< \brief (UOTGHS_DEVISR) Start of Frame Interrupt */
+#define UOTGHS_DEVISR_EORST (0x1u << 3) /**< \brief (UOTGHS_DEVISR) End of Reset Interrupt */
+#define UOTGHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (UOTGHS_DEVISR) Wake-Up Interrupt */
+#define UOTGHS_DEVISR_EORSM (0x1u << 5) /**< \brief (UOTGHS_DEVISR) End of Resume Interrupt */
+#define UOTGHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (UOTGHS_DEVISR) Upstream Resume Interrupt */
+#define UOTGHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVISR) Endpoint 0 Interrupt */
+#define UOTGHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVISR) Endpoint 1 Interrupt */
+#define UOTGHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVISR) Endpoint 2 Interrupt */
+#define UOTGHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVISR) Endpoint 3 Interrupt */
+#define UOTGHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVISR) Endpoint 4 Interrupt */
+#define UOTGHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVISR) Endpoint 5 Interrupt */
+#define UOTGHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVISR) Endpoint 6 Interrupt */
+#define UOTGHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVISR) Endpoint 7 Interrupt */
+#define UOTGHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVISR) Endpoint 8 Interrupt */
+#define UOTGHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVISR) Endpoint 9 Interrupt */
+#define UOTGHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVISR) DMA Channel 1 Interrupt */
+#define UOTGHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVISR) DMA Channel 2 Interrupt */
+#define UOTGHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVISR) DMA Channel 3 Interrupt */
+#define UOTGHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVISR) DMA Channel 4 Interrupt */
+#define UOTGHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVISR) DMA Channel 5 Interrupt */
+#define UOTGHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVISR) DMA Channel 6 Interrupt */
+/* -------- UOTGHS_DEVICR : (UOTGHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */
+#define UOTGHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (UOTGHS_DEVICR) Suspend Interrupt Clear */
+#define UOTGHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (UOTGHS_DEVICR) Micro Start of Frame Interrupt Clear */
+#define UOTGHS_DEVICR_SOFC (0x1u << 2) /**< \brief (UOTGHS_DEVICR) Start of Frame Interrupt Clear */
+#define UOTGHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (UOTGHS_DEVICR) End of Reset Interrupt Clear */
+#define UOTGHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (UOTGHS_DEVICR) Wake-Up Interrupt Clear */
+#define UOTGHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (UOTGHS_DEVICR) End of Resume Interrupt Clear */
+#define UOTGHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (UOTGHS_DEVICR) Upstream Resume Interrupt Clear */
+/* -------- UOTGHS_DEVIFR : (UOTGHS Offset: 0x000C) Device Global Interrupt Set Register -------- */
+#define UOTGHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (UOTGHS_DEVIFR) Suspend Interrupt Set */
+#define UOTGHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (UOTGHS_DEVIFR) Micro Start of Frame Interrupt Set */
+#define UOTGHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (UOTGHS_DEVIFR) Start of Frame Interrupt Set */
+#define UOTGHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (UOTGHS_DEVIFR) End of Reset Interrupt Set */
+#define UOTGHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (UOTGHS_DEVIFR) Wake-Up Interrupt Set */
+#define UOTGHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (UOTGHS_DEVIFR) End of Resume Interrupt Set */
+#define UOTGHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (UOTGHS_DEVIFR) Upstream Resume Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIFR) DMA Channel 1 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIFR) DMA Channel 2 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIFR) DMA Channel 3 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIFR) DMA Channel 4 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIFR) DMA Channel 5 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIFR) DMA Channel 6 Interrupt Set */
+/* -------- UOTGHS_DEVIMR : (UOTGHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */
+#define UOTGHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (UOTGHS_DEVIMR) Suspend Interrupt Mask */
+#define UOTGHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (UOTGHS_DEVIMR) Micro Start of Frame Interrupt Mask */
+#define UOTGHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (UOTGHS_DEVIMR) Start of Frame Interrupt Mask */
+#define UOTGHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (UOTGHS_DEVIMR) End of Reset Interrupt Mask */
+#define UOTGHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (UOTGHS_DEVIMR) Wake-Up Interrupt Mask */
+#define UOTGHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (UOTGHS_DEVIMR) End of Resume Interrupt Mask */
+#define UOTGHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (UOTGHS_DEVIMR) Upstream Resume Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIMR) Endpoint 0 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIMR) Endpoint 1 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIMR) Endpoint 2 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIMR) Endpoint 3 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIMR) Endpoint 4 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIMR) Endpoint 5 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIMR) Endpoint 6 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIMR) Endpoint 7 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIMR) Endpoint 8 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIMR) Endpoint 9 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIMR) DMA Channel 1 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIMR) DMA Channel 2 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIMR) DMA Channel 3 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIMR) DMA Channel 4 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIMR) DMA Channel 5 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIMR) DMA Channel 6 Interrupt Mask */
+/* -------- UOTGHS_DEVIDR : (UOTGHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */
+#define UOTGHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (UOTGHS_DEVIDR) Suspend Interrupt Disable */
+#define UOTGHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (UOTGHS_DEVIDR) Micro Start of Frame Interrupt Disable */
+#define UOTGHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (UOTGHS_DEVIDR) Start of Frame Interrupt Disable */
+#define UOTGHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (UOTGHS_DEVIDR) End of Reset Interrupt Disable */
+#define UOTGHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (UOTGHS_DEVIDR) Wake-Up Interrupt Disable */
+#define UOTGHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (UOTGHS_DEVIDR) End of Resume Interrupt Disable */
+#define UOTGHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (UOTGHS_DEVIDR) Upstream Resume Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIDR) Endpoint 0 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIDR) Endpoint 1 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIDR) Endpoint 2 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIDR) Endpoint 3 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIDR) Endpoint 4 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIDR) Endpoint 5 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIDR) Endpoint 6 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIDR) Endpoint 7 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIDR) Endpoint 8 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIDR) Endpoint 9 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIDR) DMA Channel 1 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIDR) DMA Channel 2 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIDR) DMA Channel 3 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIDR) DMA Channel 4 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIDR) DMA Channel 5 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIDR) DMA Channel 6 Interrupt Disable */
+/* -------- UOTGHS_DEVIER : (UOTGHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */
+#define UOTGHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (UOTGHS_DEVIER) Suspend Interrupt Enable */
+#define UOTGHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (UOTGHS_DEVIER) Micro Start of Frame Interrupt Enable */
+#define UOTGHS_DEVIER_SOFES (0x1u << 2) /**< \brief (UOTGHS_DEVIER) Start of Frame Interrupt Enable */
+#define UOTGHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (UOTGHS_DEVIER) End of Reset Interrupt Enable */
+#define UOTGHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (UOTGHS_DEVIER) Wake-Up Interrupt Enable */
+#define UOTGHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (UOTGHS_DEVIER) End of Resume Interrupt Enable */
+#define UOTGHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (UOTGHS_DEVIER) Upstream Resume Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIER) Endpoint 0 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIER) Endpoint 1 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIER) Endpoint 2 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIER) Endpoint 3 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIER) Endpoint 4 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIER) Endpoint 5 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIER) Endpoint 6 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIER) Endpoint 7 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIER) Endpoint 8 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIER) Endpoint 9 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIER) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIER) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIER) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIER) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIER) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIER) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_DEVEPT : (UOTGHS Offset: 0x001C) Device Endpoint Register -------- */
+#define UOTGHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Enable */
+#define UOTGHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Enable */
+#define UOTGHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Enable */
+#define UOTGHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Enable */
+#define UOTGHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Enable */
+#define UOTGHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Enable */
+#define UOTGHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Enable */
+#define UOTGHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Enable */
+#define UOTGHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Enable */
+#define UOTGHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Reset */
+#define UOTGHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Reset */
+#define UOTGHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Reset */
+#define UOTGHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Reset */
+#define UOTGHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Reset */
+#define UOTGHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Reset */
+#define UOTGHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Reset */
+#define UOTGHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Reset */
+#define UOTGHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Reset */
+/* -------- UOTGHS_DEVFNUM : (UOTGHS Offset: 0x0020) Device Frame Number Register -------- */
+#define UOTGHS_DEVFNUM_MFNUM_Pos 0
+#define UOTGHS_DEVFNUM_MFNUM_Msk (0x7u << UOTGHS_DEVFNUM_MFNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Micro Frame Number */
+#define UOTGHS_DEVFNUM_FNUM_Pos 3
+#define UOTGHS_DEVFNUM_FNUM_Msk (0x7ffu << UOTGHS_DEVFNUM_FNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Frame Number */
+#define UOTGHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (UOTGHS_DEVFNUM) Frame Number CRC Error */
+/* -------- UOTGHS_DEVEPTCFG[10] : (UOTGHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */
+#define UOTGHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Memory Allocate */
+#define UOTGHS_DEVEPTCFG_EPBK_Pos 2
+#define UOTGHS_DEVEPTCFG_EPBK_Msk (0x3u << UOTGHS_DEVEPTCFG_EPBK_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Banks */
+#define   UOTGHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Single-bank endpoint */
+#define   UOTGHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Double-bank endpoint */
+#define   UOTGHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Triple-bank endpoint */
+#define UOTGHS_DEVEPTCFG_EPSIZE_Pos 4
+#define UOTGHS_DEVEPTCFG_EPSIZE_Msk (0x7u << UOTGHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Size */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 8 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 16 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 32 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 64 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 128 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 256 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 512 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 1024 bytes */
+#define UOTGHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Direction */
+#define   UOTGHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is OUT. */
+#define   UOTGHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */
+#define UOTGHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (UOTGHS_DEVEPTCFG[10]) Automatic Switch */
+#define UOTGHS_DEVEPTCFG_EPTYPE_Pos 11
+#define UOTGHS_DEVEPTCFG_EPTYPE_Msk (0x3u << UOTGHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Type */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Control */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Isochronous */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Bulk */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Interrupt */
+#define UOTGHS_DEVEPTCFG_NBTRANS_Pos 13
+#define UOTGHS_DEVEPTCFG_NBTRANS_Msk (0x3u << UOTGHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Number of transaction per microframe for isochronous endpoint */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) reserved to endpoint that does not have the high-bandwidth isochronous capability. */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) default value: one transaction per micro-frame. */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 2 transactions per micro-frame. This endpoint should be configured as double-bank. */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 3 transactions per micro-frame. This endpoint should be configured as triple-bank. */
+/* -------- UOTGHS_DEVEPTISR[10] : (UOTGHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */
+#define UOTGHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (UOTGHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */
+#define UOTGHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (UOTGHS_DEVEPTISR[10]) Received OUT Data Interrupt */
+#define UOTGHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Received SETUP Interrupt */
+#define UOTGHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Underflow Interrupt */
+#define UOTGHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed OUT Interrupt */
+#define UOTGHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) High bandwidth isochronous IN Underflow Error Interrupt */
+#define UOTGHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed IN Interrupt */
+#define UOTGHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */
+#define UOTGHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_DEVEPTISR[10]) Overflow Interrupt */
+#define UOTGHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) STALLed Interrupt */
+#define UOTGHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) CRC Error Interrupt */
+#define UOTGHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (UOTGHS_DEVEPTISR[10]) Short Packet Interrupt */
+#define UOTGHS_DEVEPTISR_DTSEQ_Pos 8
+#define UOTGHS_DEVEPTISR_DTSEQ_Msk (0x3u << UOTGHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Data Toggle Sequence */
+#define   UOTGHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data0 toggle sequence */
+#define   UOTGHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data1 toggle sequence */
+#define   UOTGHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data2 toggle sequence (for high-bandwidth isochronous endpoint) */
+#define   UOTGHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) MData toggle sequence (for high-bandwidth isochronous endpoint) */
+#define UOTGHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (UOTGHS_DEVEPTISR[10]) High-bandwidth isochronous OUT endpoint transaction error Interrupt */
+#define UOTGHS_DEVEPTISR_NBUSYBK_Pos 12
+#define UOTGHS_DEVEPTISR_NBUSYBK_Msk (0x3u << UOTGHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Number of Busy Banks */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 0 busy bank (all banks free) */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 1 busy bank */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 2 busy banks */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 3 busy banks */
+#define UOTGHS_DEVEPTISR_CURRBK_Pos 14
+#define UOTGHS_DEVEPTISR_CURRBK_Msk (0x3u << UOTGHS_DEVEPTISR_CURRBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Current Bank */
+#define   UOTGHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank0 */
+#define   UOTGHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank1 */
+#define   UOTGHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank2 */
+#define UOTGHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_DEVEPTISR[10]) Read-write Allowed */
+#define UOTGHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (UOTGHS_DEVEPTISR[10]) Control Direction */
+#define UOTGHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_DEVEPTISR[10]) Configuration OK Status */
+#define UOTGHS_DEVEPTISR_BYCT_Pos 20
+#define UOTGHS_DEVEPTISR_BYCT_Msk (0x7ffu << UOTGHS_DEVEPTISR_BYCT_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Byte Count */
+/* -------- UOTGHS_DEVEPTICR[10] : (UOTGHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */
+#define UOTGHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */
+#define UOTGHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */
+#define UOTGHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */
+#define UOTGHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Underflow Interrupt Clear */
+#define UOTGHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */
+#define UOTGHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) High bandwidth isochronous IN Underflow Error Interrupt Clear */
+#define UOTGHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */
+#define UOTGHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
+#define UOTGHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTICR[10]) Overflow Interrupt Clear */
+#define UOTGHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) STALLed Interrupt Clear */
+#define UOTGHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTICR[10]) Short Packet Interrupt Clear */
+/* -------- UOTGHS_DEVEPTIFR[10] : (UOTGHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */
+#define UOTGHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */
+#define UOTGHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */
+#define UOTGHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Underflow Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */
+#define UOTGHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) High bandwidth isochronous IN Underflow Error Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */
+#define UOTGHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */
+#define UOTGHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIFR[10]) Overflow Interrupt Set */
+#define UOTGHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) STALLed Interrupt Set */
+#define UOTGHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) CRC Error Interrupt Set */
+#define UOTGHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIFR[10]) Short Packet Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */
+/* -------- UOTGHS_DEVEPTIMR[10] : (UOTGHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */
+#define UOTGHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received OUT Data Interrupt */
+#define UOTGHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received SETUP Interrupt */
+#define UOTGHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Underflow Interrupt */
+#define UOTGHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed OUT Interrupt */
+#define UOTGHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */
+#define UOTGHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed IN Interrupt */
+#define UOTGHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */
+#define UOTGHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIMR[10]) Overflow Interrupt */
+#define UOTGHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALLed Interrupt */
+#define UOTGHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) CRC Error Interrupt */
+#define UOTGHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIMR[10]) Short Packet Interrupt */
+#define UOTGHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIMR[10]) MData Interrupt */
+#define UOTGHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIMR[10]) DataX Interrupt */
+#define UOTGHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transaction Error Interrupt */
+#define UOTGHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */
+#define UOTGHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIMR[10]) Kill IN Bank */
+#define UOTGHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIMR[10]) FIFO Control */
+#define UOTGHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */
+#define UOTGHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIMR[10]) NYET Token Disable */
+#define UOTGHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIMR[10]) Reset Data Toggle */
+#define UOTGHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALL Request */
+/* -------- UOTGHS_DEVEPTIER[10] : (UOTGHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */
+#define UOTGHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */
+#define UOTGHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */
+#define UOTGHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Underflow Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */
+#define UOTGHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */
+#define UOTGHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */
+#define UOTGHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIER[10]) Overflow Interrupt Enable */
+#define UOTGHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) STALLed Interrupt Enable */
+#define UOTGHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) CRC Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIER[10]) Short Packet Interrupt Enable */
+#define UOTGHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIER[10]) MData Interrupt Enable */
+#define UOTGHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIER[10]) DataX Interrupt Enable */
+#define UOTGHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */
+#define UOTGHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIER[10]) Kill IN Bank */
+#define UOTGHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */
+#define UOTGHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIER[10]) NYET Token Disable Enable */
+#define UOTGHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIER[10]) Reset Data Toggle Enable */
+#define UOTGHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIER[10]) STALL Request Enable */
+/* -------- UOTGHS_DEVEPTIDR[10] : (UOTGHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Underflow Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIDR[10]) Overflow Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALLed Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIDR[10]) MData Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIDR[10]) DataX Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIDR[10]) FIFO Control Clear */
+#define UOTGHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */
+#define UOTGHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIDR[10]) NYET Token Disable Clear */
+#define UOTGHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALL Request Clear */
+/* -------- UOTGHS_DEVDMANXTDSC : (UOTGHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_DEVDMANXTDSC) Next Descriptor Address */
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UOTGHS_DEVDMAADDRESS : (UOTGHS Offset: N/A) Device DMA Channel Address Register -------- */
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos 0
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_DEVDMAADDRESS) Buffer Address */
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD(value) ((UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UOTGHS_DEVDMACONTROL : (UOTGHS Offset: N/A) Device DMA Channel Control Register -------- */
+#define UOTGHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMACONTROL) Channel Enable Command */
+#define UOTGHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
+#define UOTGHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Enable Control */
+#define UOTGHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Enable Control */
+#define UOTGHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_DEVDMACONTROL) Burst Lock Enable */
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UOTGHS_DEVDMASTATUS : (UOTGHS Offset: N/A) Device DMA Channel Status Register -------- */
+#define UOTGHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Enable Status */
+#define UOTGHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Active Status */
+#define UOTGHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Transfer Status */
+#define UOTGHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Buffer Status */
+#define UOTGHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_DEVDMASTATUS) Descriptor Loaded Status */
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos 16
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_DEVDMASTATUS) Buffer Byte Count */
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT(value) ((UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos)))
+/* -------- UOTGHS_HSTCTRL : (UOTGHS Offset: 0x0400) Host General Control Register -------- */
+#define UOTGHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (UOTGHS_HSTCTRL) Start of Frame Generation Enable */
+#define UOTGHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (UOTGHS_HSTCTRL) Send USB Reset */
+#define UOTGHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (UOTGHS_HSTCTRL) Send USB Resume */
+#define UOTGHS_HSTCTRL_SPDCONF_Pos 12
+#define UOTGHS_HSTCTRL_SPDCONF_Msk (0x3u << UOTGHS_HSTCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_HSTCTRL) Mode Configuration */
+#define   UOTGHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (UOTGHS_HSTCTRL) The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. */
+#define   UOTGHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (UOTGHS_HSTCTRL) For a better consumption, if high-speed is not needed. */
+#define   UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (UOTGHS_HSTCTRL) Forced high speed. */
+#define   UOTGHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (UOTGHS_HSTCTRL) The host remains to full-speed mode whatever the peripheral speed capability. */
+/* -------- UOTGHS_HSTISR : (UOTGHS Offset: 0x0404) Host Global Interrupt Status Register -------- */
+#define UOTGHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (UOTGHS_HSTISR) Device Connection Interrupt */
+#define UOTGHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (UOTGHS_HSTISR) Device Disconnection Interrupt */
+#define UOTGHS_HSTISR_RSTI (0x1u << 2) /**< \brief (UOTGHS_HSTISR) USB Reset Sent Interrupt */
+#define UOTGHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (UOTGHS_HSTISR) Downstream Resume Sent Interrupt */
+#define UOTGHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (UOTGHS_HSTISR) Upstream Resume Received Interrupt */
+#define UOTGHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (UOTGHS_HSTISR) Host Start of Frame Interrupt */
+#define UOTGHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (UOTGHS_HSTISR) Host Wake-Up Interrupt */
+#define UOTGHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTISR) Pipe 0 Interrupt */
+#define UOTGHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTISR) Pipe 1 Interrupt */
+#define UOTGHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTISR) Pipe 2 Interrupt */
+#define UOTGHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTISR) Pipe 3 Interrupt */
+#define UOTGHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTISR) Pipe 4 Interrupt */
+#define UOTGHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTISR) Pipe 5 Interrupt */
+#define UOTGHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTISR) Pipe 6 Interrupt */
+#define UOTGHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTISR) Pipe 7 Interrupt */
+#define UOTGHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTISR) Pipe 8 Interrupt */
+#define UOTGHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTISR) Pipe 9 Interrupt */
+#define UOTGHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTISR) DMA Channel 1 Interrupt */
+#define UOTGHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTISR) DMA Channel 2 Interrupt */
+#define UOTGHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTISR) DMA Channel 3 Interrupt */
+#define UOTGHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTISR) DMA Channel 4 Interrupt */
+#define UOTGHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTISR) DMA Channel 5 Interrupt */
+#define UOTGHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTISR) DMA Channel 6 Interrupt */
+/* -------- UOTGHS_HSTICR : (UOTGHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */
+#define UOTGHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (UOTGHS_HSTICR) Device Connection Interrupt Clear */
+#define UOTGHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (UOTGHS_HSTICR) Device Disconnection Interrupt Clear */
+#define UOTGHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (UOTGHS_HSTICR) USB Reset Sent Interrupt Clear */
+#define UOTGHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (UOTGHS_HSTICR) Downstream Resume Sent Interrupt Clear */
+#define UOTGHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (UOTGHS_HSTICR) Upstream Resume Received Interrupt Clear */
+#define UOTGHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (UOTGHS_HSTICR) Host Start of Frame Interrupt Clear */
+#define UOTGHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (UOTGHS_HSTICR) Host Wake-Up Interrupt Clear */
+/* -------- UOTGHS_HSTIFR : (UOTGHS Offset: 0x040C) Host Global Interrupt Set Register -------- */
+#define UOTGHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (UOTGHS_HSTIFR) Device Connection Interrupt Set */
+#define UOTGHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (UOTGHS_HSTIFR) Device Disconnection Interrupt Set */
+#define UOTGHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (UOTGHS_HSTIFR) USB Reset Sent Interrupt Set */
+#define UOTGHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (UOTGHS_HSTIFR) Downstream Resume Sent Interrupt Set */
+#define UOTGHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (UOTGHS_HSTIFR) Upstream Resume Received Interrupt Set */
+#define UOTGHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (UOTGHS_HSTIFR) Host Start of Frame Interrupt Set */
+#define UOTGHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (UOTGHS_HSTIFR) Host Wake-Up Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIFR) DMA Channel 1 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIFR) DMA Channel 2 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIFR) DMA Channel 3 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIFR) DMA Channel 4 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIFR) DMA Channel 5 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIFR) DMA Channel 6 Interrupt Set */
+/* -------- UOTGHS_HSTIMR : (UOTGHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */
+#define UOTGHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (UOTGHS_HSTIMR) Device Connection Interrupt Enable */
+#define UOTGHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (UOTGHS_HSTIMR) Device Disconnection Interrupt Enable */
+#define UOTGHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (UOTGHS_HSTIMR) USB Reset Sent Interrupt Enable */
+#define UOTGHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (UOTGHS_HSTIMR) Downstream Resume Sent Interrupt Enable */
+#define UOTGHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (UOTGHS_HSTIMR) Upstream Resume Received Interrupt Enable */
+#define UOTGHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (UOTGHS_HSTIMR) Host Start of Frame Interrupt Enable */
+#define UOTGHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (UOTGHS_HSTIMR) Host Wake-Up Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIMR) Pipe 0 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIMR) Pipe 1 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIMR) Pipe 2 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIMR) Pipe 3 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIMR) Pipe 4 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIMR) Pipe 5 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIMR) Pipe 6 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIMR) Pipe 7 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIMR) Pipe 8 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIMR) Pipe 9 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIMR) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIMR) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIMR) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIMR) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIMR) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIMR) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_HSTIDR : (UOTGHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */
+#define UOTGHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (UOTGHS_HSTIDR) Device Connection Interrupt Disable */
+#define UOTGHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (UOTGHS_HSTIDR) Device Disconnection Interrupt Disable */
+#define UOTGHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (UOTGHS_HSTIDR) USB Reset Sent Interrupt Disable */
+#define UOTGHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (UOTGHS_HSTIDR) Downstream Resume Sent Interrupt Disable */
+#define UOTGHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (UOTGHS_HSTIDR) Upstream Resume Received Interrupt Disable */
+#define UOTGHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTIDR) Host Start of Frame Interrupt Disable */
+#define UOTGHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (UOTGHS_HSTIDR) Host Wake-Up Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIDR) Pipe 0 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIDR) Pipe 1 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIDR) Pipe 2 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIDR) Pipe 3 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIDR) Pipe 4 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIDR) Pipe 5 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIDR) Pipe 6 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIDR) Pipe 7 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIDR) Pipe 8 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIDR) Pipe 9 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIDR) DMA Channel 1 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIDR) DMA Channel 2 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIDR) DMA Channel 3 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIDR) DMA Channel 4 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIDR) DMA Channel 5 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIDR) DMA Channel 6 Interrupt Disable */
+/* -------- UOTGHS_HSTIER : (UOTGHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */
+#define UOTGHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (UOTGHS_HSTIER) Device Connection Interrupt Enable */
+#define UOTGHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (UOTGHS_HSTIER) Device Disconnection Interrupt Enable */
+#define UOTGHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (UOTGHS_HSTIER) USB Reset Sent Interrupt Enable */
+#define UOTGHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (UOTGHS_HSTIER) Downstream Resume Sent Interrupt Enable */
+#define UOTGHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (UOTGHS_HSTIER) Upstream Resume Received Interrupt Enable */
+#define UOTGHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (UOTGHS_HSTIER) Host Start of Frame Interrupt Enable */
+#define UOTGHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (UOTGHS_HSTIER) Host Wake-Up Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIER) Pipe 0 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIER) Pipe 1 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIER) Pipe 2 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIER) Pipe 3 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIER) Pipe 4 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIER) Pipe 5 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIER) Pipe 6 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIER) Pipe 7 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIER) Pipe 8 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIER) Pipe 9 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIER) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIER) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIER) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIER) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIER) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIER) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_HSTPIP : (UOTGHS Offset: 0x0041C) Host Pipe Register -------- */
+#define UOTGHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Enable */
+#define UOTGHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Enable */
+#define UOTGHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Enable */
+#define UOTGHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Enable */
+#define UOTGHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Enable */
+#define UOTGHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Enable */
+#define UOTGHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Enable */
+#define UOTGHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Enable */
+#define UOTGHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Enable */
+#define UOTGHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Reset */
+#define UOTGHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Reset */
+#define UOTGHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Reset */
+#define UOTGHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Reset */
+#define UOTGHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Reset */
+#define UOTGHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Reset */
+#define UOTGHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Reset */
+#define UOTGHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Reset */
+#define UOTGHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Reset */
+/* -------- UOTGHS_HSTFNUM : (UOTGHS Offset: 0x0420) Host Frame Number Register -------- */
+#define UOTGHS_HSTFNUM_MFNUM_Pos 0
+#define UOTGHS_HSTFNUM_MFNUM_Msk (0x7u << UOTGHS_HSTFNUM_MFNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Micro Frame Number */
+#define UOTGHS_HSTFNUM_MFNUM(value) ((UOTGHS_HSTFNUM_MFNUM_Msk & ((value) << UOTGHS_HSTFNUM_MFNUM_Pos)))
+#define UOTGHS_HSTFNUM_FNUM_Pos 3
+#define UOTGHS_HSTFNUM_FNUM_Msk (0x7ffu << UOTGHS_HSTFNUM_FNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Number */
+#define UOTGHS_HSTFNUM_FNUM(value) ((UOTGHS_HSTFNUM_FNUM_Msk & ((value) << UOTGHS_HSTFNUM_FNUM_Pos)))
+#define UOTGHS_HSTFNUM_FLENHIGH_Pos 16
+#define UOTGHS_HSTFNUM_FLENHIGH_Msk (0xffu << UOTGHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Length */
+#define UOTGHS_HSTFNUM_FLENHIGH(value) ((UOTGHS_HSTFNUM_FLENHIGH_Msk & ((value) << UOTGHS_HSTFNUM_FLENHIGH_Pos)))
+/* -------- UOTGHS_HSTADDR1 : (UOTGHS Offset: 0x0424) Host Address 1 Register -------- */
+#define UOTGHS_HSTADDR1_HSTADDRP0_Pos 0
+#define UOTGHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP0(value) ((UOTGHS_HSTADDR1_HSTADDRP0_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP0_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP1_Pos 8
+#define UOTGHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP1(value) ((UOTGHS_HSTADDR1_HSTADDRP1_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP1_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP2_Pos 16
+#define UOTGHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP2(value) ((UOTGHS_HSTADDR1_HSTADDRP2_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP2_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP3_Pos 24
+#define UOTGHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP3(value) ((UOTGHS_HSTADDR1_HSTADDRP3_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP3_Pos)))
+/* -------- UOTGHS_HSTADDR2 : (UOTGHS Offset: 0x0428) Host Address 2 Register -------- */
+#define UOTGHS_HSTADDR2_HSTADDRP4_Pos 0
+#define UOTGHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP4(value) ((UOTGHS_HSTADDR2_HSTADDRP4_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP4_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP5_Pos 8
+#define UOTGHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP5(value) ((UOTGHS_HSTADDR2_HSTADDRP5_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP5_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP6_Pos 16
+#define UOTGHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP6(value) ((UOTGHS_HSTADDR2_HSTADDRP6_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP6_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP7_Pos 24
+#define UOTGHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP7(value) ((UOTGHS_HSTADDR2_HSTADDRP7_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP7_Pos)))
+/* -------- UOTGHS_HSTADDR3 : (UOTGHS Offset: 0x042C) Host Address 3 Register -------- */
+#define UOTGHS_HSTADDR3_HSTADDRP8_Pos 0
+#define UOTGHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */
+#define UOTGHS_HSTADDR3_HSTADDRP8(value) ((UOTGHS_HSTADDR3_HSTADDRP8_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP8_Pos)))
+#define UOTGHS_HSTADDR3_HSTADDRP9_Pos 8
+#define UOTGHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */
+#define UOTGHS_HSTADDR3_HSTADDRP9(value) ((UOTGHS_HSTADDR3_HSTADDRP9_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP9_Pos)))
+/* -------- UOTGHS_HSTPIPCFG[10] : (UOTGHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */
+#define UOTGHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Memory Allocate */
+#define UOTGHS_HSTPIPCFG_PBK_Pos 2
+#define UOTGHS_HSTPIPCFG_PBK_Msk (0x3u << UOTGHS_HSTPIPCFG_PBK_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Banks */
+#define   UOTGHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Single-bank pipe */
+#define   UOTGHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Double-bank pipe */
+#define   UOTGHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Triple-bank pipe */
+#define UOTGHS_HSTPIPCFG_PSIZE_Pos 4
+#define UOTGHS_HSTPIPCFG_PSIZE_Msk (0x7u << UOTGHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Size */
+#define   UOTGHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 8 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 16 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 32 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 64 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 128 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 256 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 512 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 1024 bytes */
+#define UOTGHS_HSTPIPCFG_PTOKEN_Pos 8
+#define UOTGHS_HSTPIPCFG_PTOKEN_Msk (0x3u << UOTGHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Token */
+#define   UOTGHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) SETUP */
+#define   UOTGHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) IN */
+#define   UOTGHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) OUT */
+#define UOTGHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (UOTGHS_HSTPIPCFG[10]) Automatic Switch */
+#define UOTGHS_HSTPIPCFG_PTYPE_Pos 12
+#define UOTGHS_HSTPIPCFG_PTYPE_Msk (0x3u << UOTGHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Type */
+#define   UOTGHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Control */
+#define   UOTGHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Isochronous */
+#define   UOTGHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Bulk */
+#define   UOTGHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Interrupt */
+#define UOTGHS_HSTPIPCFG_PEPNUM_Pos 16
+#define UOTGHS_HSTPIPCFG_PEPNUM_Msk (0xfu << UOTGHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Endpoint Number */
+#define UOTGHS_HSTPIPCFG_PEPNUM(value) ((UOTGHS_HSTPIPCFG_PEPNUM_Msk & ((value) << UOTGHS_HSTPIPCFG_PEPNUM_Pos)))
+#define UOTGHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (UOTGHS_HSTPIPCFG[10]) Ping Enable */
+#define UOTGHS_HSTPIPCFG_INTFRQ_Pos 24
+#define UOTGHS_HSTPIPCFG_INTFRQ_Msk (0xffu << UOTGHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */
+#define UOTGHS_HSTPIPCFG_INTFRQ(value) ((UOTGHS_HSTPIPCFG_INTFRQ_Msk & ((value) << UOTGHS_HSTPIPCFG_INTFRQ_Pos)))
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Pos 24
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << UOTGHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) bInterval parameter for the Bulk-Out/Ping transaction */
+#define UOTGHS_HSTPIPCFG_BINTERVAL(value) ((UOTGHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << UOTGHS_HSTPIPCFG_BINTERVAL_Pos)))
+/* -------- UOTGHS_HSTPIPISR[10] : (UOTGHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */
+#define UOTGHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (UOTGHS_HSTPIPISR[10]) Received IN Data Interrupt */
+#define UOTGHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */
+#define UOTGHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */
+#define UOTGHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Underflow Interrupt */
+#define UOTGHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Error Interrupt */
+#define UOTGHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (UOTGHS_HSTPIPISR[10]) NAKed Interrupt */
+#define UOTGHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_HSTPIPISR[10]) Overflow Interrupt */
+#define UOTGHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) Received STALLed Interrupt */
+#define UOTGHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) CRC Error Interrupt */
+#define UOTGHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (UOTGHS_HSTPIPISR[10]) Short Packet Interrupt */
+#define UOTGHS_HSTPIPISR_DTSEQ_Pos 8
+#define UOTGHS_HSTPIPISR_DTSEQ_Msk (0x3u << UOTGHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Data Toggle Sequence */
+#define   UOTGHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data0 toggle sequence */
+#define   UOTGHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data1 toggle sequence */
+#define UOTGHS_HSTPIPISR_NBUSYBK_Pos 12
+#define UOTGHS_HSTPIPISR_NBUSYBK_Msk (0x3u << UOTGHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Number of Busy Banks */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 0 busy bank (all banks free) */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 1 busy bank */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 2 busy banks */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 3 busy banks */
+#define UOTGHS_HSTPIPISR_CURRBK_Pos 14
+#define UOTGHS_HSTPIPISR_CURRBK_Msk (0x3u << UOTGHS_HSTPIPISR_CURRBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Current Bank */
+#define   UOTGHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank0 */
+#define   UOTGHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank1 */
+#define   UOTGHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank2 */
+#define UOTGHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_HSTPIPISR[10]) Read-write Allowed */
+#define UOTGHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_HSTPIPISR[10]) Configuration OK Status */
+#define UOTGHS_HSTPIPISR_PBYCT_Pos 20
+#define UOTGHS_HSTPIPISR_PBYCT_Msk (0x7ffu << UOTGHS_HSTPIPISR_PBYCT_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Byte Count */
+/* -------- UOTGHS_HSTPIPICR[10] : (UOTGHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */
+#define UOTGHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */
+#define UOTGHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */
+#define UOTGHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */
+#define UOTGHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Underflow Interrupt Clear */
+#define UOTGHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPICR[10]) NAKed Interrupt Clear */
+#define UOTGHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPICR[10]) Overflow Interrupt Clear */
+#define UOTGHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */
+#define UOTGHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPICR[10]) Short Packet Interrupt Clear */
+/* -------- UOTGHS_HSTPIPIFR[10] : (UOTGHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */
+#define UOTGHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */
+#define UOTGHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */
+#define UOTGHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Underflow Interrupt Set */
+#define UOTGHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */
+#define UOTGHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIFR[10]) NAKed Interrupt Set */
+#define UOTGHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIFR[10]) Overflow Interrupt Set */
+#define UOTGHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */
+#define UOTGHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) CRC Error Interrupt Set */
+#define UOTGHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIFR[10]) Short Packet Interrupt Set */
+#define UOTGHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIFR[10]) Number of Busy Banks Set */
+/* -------- UOTGHS_HSTPIPIMR[10] : (UOTGHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Underflow Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIMR[10]) NAKed Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIMR[10]) Overflow Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIMR[10]) FIFO Control */
+#define UOTGHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */
+#define UOTGHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Freeze */
+#define UOTGHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIMR[10]) Reset Data Toggle */
+/* -------- UOTGHS_HSTPIPIER[10] : (UOTGHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */
+#define UOTGHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */
+#define UOTGHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */
+#define UOTGHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Underflow Interrupt Enable */
+#define UOTGHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */
+#define UOTGHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIER[10]) NAKed Interrupt Enable */
+#define UOTGHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIER[10]) Overflow Interrupt Enable */
+#define UOTGHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */
+#define UOTGHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) CRC Error Interrupt Enable */
+#define UOTGHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIER[10]) Short Packet Interrupt Enable */
+#define UOTGHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIER[10]) Number of Busy Banks Enable */
+#define UOTGHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */
+#define UOTGHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Freeze Enable */
+#define UOTGHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIER[10]) Reset Data Toggle Enable */
+/* -------- UOTGHS_HSTPIPIDR[10] : (UOTGHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Underflow Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIDR[10]) NAKed Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIDR[10]) Overflow Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIDR[10]) Number of Busy Banks Disable */
+#define UOTGHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIDR[10]) FIFO Control Disable */
+#define UOTGHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */
+#define UOTGHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Freeze Disable */
+/* -------- UOTGHS_HSTPIPINRQ[10] : (UOTGHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */
+#define UOTGHS_HSTPIPINRQ_INRQ_Pos 0
+#define UOTGHS_HSTPIPINRQ_INRQ_Msk (0xffu << UOTGHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Number before Freeze */
+#define UOTGHS_HSTPIPINRQ_INRQ(value) ((UOTGHS_HSTPIPINRQ_INRQ_Msk & ((value) << UOTGHS_HSTPIPINRQ_INRQ_Pos)))
+#define UOTGHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Mode */
+/* -------- UOTGHS_HSTPIPERR[10] : (UOTGHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */
+#define UOTGHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (UOTGHS_HSTPIPERR[10]) Data Toggle Error */
+#define UOTGHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (UOTGHS_HSTPIPERR[10]) Data PID Error */
+#define UOTGHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (UOTGHS_HSTPIPERR[10]) PID Error */
+#define UOTGHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (UOTGHS_HSTPIPERR[10]) Time-Out Error */
+#define UOTGHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (UOTGHS_HSTPIPERR[10]) CRC16 Error */
+#define UOTGHS_HSTPIPERR_COUNTER_Pos 5
+#define UOTGHS_HSTPIPERR_COUNTER_Msk (0x3u << UOTGHS_HSTPIPERR_COUNTER_Pos) /**< \brief (UOTGHS_HSTPIPERR[10]) Error Counter */
+#define UOTGHS_HSTPIPERR_COUNTER(value) ((UOTGHS_HSTPIPERR_COUNTER_Msk & ((value) << UOTGHS_HSTPIPERR_COUNTER_Pos)))
+/* -------- UOTGHS_HSTDMANXTDSC : (UOTGHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_HSTDMANXTDSC) Next Descriptor Address */
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UOTGHS_HSTDMAADDRESS : (UOTGHS Offset: N/A) Host DMA Channel Address Register -------- */
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos 0
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_HSTDMAADDRESS) Buffer Address */
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD(value) ((UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UOTGHS_HSTDMACONTROL : (UOTGHS Offset: N/A) Host DMA Channel Control Register -------- */
+#define UOTGHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMACONTROL) Channel Enable Command */
+#define UOTGHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
+#define UOTGHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Enable (Control) */
+#define UOTGHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Enable Control */
+#define UOTGHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_HSTDMACONTROL) Burst Lock Enable */
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UOTGHS_HSTDMASTATUS : (UOTGHS Offset: N/A) Host DMA Channel Status Register -------- */
+#define UOTGHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Enable Status */
+#define UOTGHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Active Status */
+#define UOTGHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Transfer Status */
+#define UOTGHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Buffer Status */
+#define UOTGHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_HSTDMASTATUS) Descriptor Loaded Status */
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos 16
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_HSTDMASTATUS) Buffer Byte Count */
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT(value) ((UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos)))
+/* -------- UOTGHS_CTRL : (UOTGHS Offset: 0x0800) General Control Register -------- */
+#define UOTGHS_CTRL_IDTE (0x1u << 0) /**< \brief (UOTGHS_CTRL) ID Transition Interrupt Enable */
+#define UOTGHS_CTRL_VBUSTE (0x1u << 1) /**< \brief (UOTGHS_CTRL) VBus Transition Interrupt Enable */
+#define UOTGHS_CTRL_SRPE (0x1u << 2) /**< \brief (UOTGHS_CTRL) SRP Interrupt Enable */
+#define UOTGHS_CTRL_VBERRE (0x1u << 3) /**< \brief (UOTGHS_CTRL) VBus Error Interrupt Enable */
+#define UOTGHS_CTRL_BCERRE (0x1u << 4) /**< \brief (UOTGHS_CTRL) B-Connection Error Interrupt Enable */
+#define UOTGHS_CTRL_ROLEEXE (0x1u << 5) /**< \brief (UOTGHS_CTRL) Role Exchange Interrupt Enable */
+#define UOTGHS_CTRL_HNPERRE (0x1u << 6) /**< \brief (UOTGHS_CTRL) HNP Error Interrupt Enable */
+#define UOTGHS_CTRL_STOE (0x1u << 7) /**< \brief (UOTGHS_CTRL) Suspend Time-Out Interrupt Enable */
+#define UOTGHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (UOTGHS_CTRL) VBus Hardware Control */
+#define UOTGHS_CTRL_SRPSEL (0x1u << 9) /**< \brief (UOTGHS_CTRL) SRP Selection */
+#define UOTGHS_CTRL_SRPREQ (0x1u << 10) /**< \brief (UOTGHS_CTRL) SRP Request */
+#define UOTGHS_CTRL_HNPREQ (0x1u << 11) /**< \brief (UOTGHS_CTRL) HNP Request */
+#define UOTGHS_CTRL_OTGPADE (0x1u << 12) /**< \brief (UOTGHS_CTRL) OTG Pad Enable */
+#define UOTGHS_CTRL_VBUSPO (0x1u << 13) /**< \brief (UOTGHS_CTRL) VBus Polarity Off */
+#define UOTGHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (UOTGHS_CTRL) Freeze USB Clock */
+#define UOTGHS_CTRL_USBE (0x1u << 15) /**< \brief (UOTGHS_CTRL) UOTGHS Enable */
+#define UOTGHS_CTRL_TIMVALUE_Pos 16
+#define UOTGHS_CTRL_TIMVALUE_Msk (0x3u << UOTGHS_CTRL_TIMVALUE_Pos) /**< \brief (UOTGHS_CTRL) Timer Value */
+#define UOTGHS_CTRL_TIMVALUE(value) ((UOTGHS_CTRL_TIMVALUE_Msk & ((value) << UOTGHS_CTRL_TIMVALUE_Pos)))
+#define UOTGHS_CTRL_TIMPAGE_Pos 20
+#define UOTGHS_CTRL_TIMPAGE_Msk (0x3u << UOTGHS_CTRL_TIMPAGE_Pos) /**< \brief (UOTGHS_CTRL) Timer Page */
+#define UOTGHS_CTRL_TIMPAGE(value) ((UOTGHS_CTRL_TIMPAGE_Msk & ((value) << UOTGHS_CTRL_TIMPAGE_Pos)))
+#define UOTGHS_CTRL_UNLOCK (0x1u << 22) /**< \brief (UOTGHS_CTRL) Timer Access Unlock */
+#define UOTGHS_CTRL_UIDE (0x1u << 24) /**< \brief (UOTGHS_CTRL) UOTGID Pin Enable */
+#define   UOTGHS_CTRL_UIDE_UIMOD (0x0u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UIMOD bit. */
+#define   UOTGHS_CTRL_UIDE_UOTGID (0x1u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UOTGID input pin. */
+#define UOTGHS_CTRL_UIMOD (0x1u << 25) /**< \brief (UOTGHS_CTRL) UOTGHS Mode */
+#define   UOTGHS_CTRL_UIMOD_Host (0x0u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB host mode. */
+#define   UOTGHS_CTRL_UIMOD_Device (0x1u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB device mode. */
+/* -------- UOTGHS_SR : (UOTGHS Offset: 0x0804) General Status Register -------- */
+#define UOTGHS_SR_IDTI (0x1u << 0) /**< \brief (UOTGHS_SR) ID Transition Interrupt */
+#define UOTGHS_SR_VBUSTI (0x1u << 1) /**< \brief (UOTGHS_SR) VBus Transition Interrupt */
+#define UOTGHS_SR_SRPI (0x1u << 2) /**< \brief (UOTGHS_SR) SRP Interrupt */
+#define UOTGHS_SR_VBERRI (0x1u << 3) /**< \brief (UOTGHS_SR) VBus Error Interrupt */
+#define UOTGHS_SR_BCERRI (0x1u << 4) /**< \brief (UOTGHS_SR) B-Connection Error Interrupt */
+#define UOTGHS_SR_ROLEEXI (0x1u << 5) /**< \brief (UOTGHS_SR) Role Exchange Interrupt */
+#define UOTGHS_SR_HNPERRI (0x1u << 6) /**< \brief (UOTGHS_SR) HNP Error Interrupt */
+#define UOTGHS_SR_STOI (0x1u << 7) /**< \brief (UOTGHS_SR) Suspend Time-Out Interrupt */
+#define UOTGHS_SR_VBUSRQ (0x1u << 9) /**< \brief (UOTGHS_SR) VBus Request */
+#define UOTGHS_SR_ID (0x1u << 10) /**< \brief (UOTGHS_SR) UOTGID Pin State */
+#define UOTGHS_SR_VBUS (0x1u << 11) /**< \brief (UOTGHS_SR) VBus Level */
+#define UOTGHS_SR_SPEED_Pos 12
+#define UOTGHS_SR_SPEED_Msk (0x3u << UOTGHS_SR_SPEED_Pos) /**< \brief (UOTGHS_SR) Speed Status */
+#define   UOTGHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (UOTGHS_SR) Full-Speed mode */
+#define   UOTGHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (UOTGHS_SR) High-Speed mode */
+#define   UOTGHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (UOTGHS_SR) Low-Speed mode */
+#define UOTGHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (UOTGHS_SR) UTMI Clock Usable */
+/* -------- UOTGHS_SCR : (UOTGHS Offset: 0x0808) General Status Clear Register -------- */
+#define UOTGHS_SCR_IDTIC (0x1u << 0) /**< \brief (UOTGHS_SCR) ID Transition Interrupt Clear */
+#define UOTGHS_SCR_VBUSTIC (0x1u << 1) /**< \brief (UOTGHS_SCR) VBus Transition Interrupt Clear */
+#define UOTGHS_SCR_SRPIC (0x1u << 2) /**< \brief (UOTGHS_SCR) SRP Interrupt Clear */
+#define UOTGHS_SCR_VBERRIC (0x1u << 3) /**< \brief (UOTGHS_SCR) VBus Error Interrupt Clear */
+#define UOTGHS_SCR_BCERRIC (0x1u << 4) /**< \brief (UOTGHS_SCR) B-Connection Error Interrupt Clear */
+#define UOTGHS_SCR_ROLEEXIC (0x1u << 5) /**< \brief (UOTGHS_SCR) Role Exchange Interrupt Clear */
+#define UOTGHS_SCR_HNPERRIC (0x1u << 6) /**< \brief (UOTGHS_SCR) HNP Error Interrupt Clear */
+#define UOTGHS_SCR_STOIC (0x1u << 7) /**< \brief (UOTGHS_SCR) Suspend Time-Out Interrupt Clear */
+#define UOTGHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (UOTGHS_SCR) VBus Request Clear */
+/* -------- UOTGHS_SFR : (UOTGHS Offset: 0x080C) General Status Set Register -------- */
+#define UOTGHS_SFR_IDTIS (0x1u << 0) /**< \brief (UOTGHS_SFR) ID Transition Interrupt Set */
+#define UOTGHS_SFR_VBUSTIS (0x1u << 1) /**< \brief (UOTGHS_SFR) VBus Transition Interrupt Set */
+#define UOTGHS_SFR_SRPIS (0x1u << 2) /**< \brief (UOTGHS_SFR) SRP Interrupt Set */
+#define UOTGHS_SFR_VBERRIS (0x1u << 3) /**< \brief (UOTGHS_SFR) VBus Error Interrupt Set */
+#define UOTGHS_SFR_BCERRIS (0x1u << 4) /**< \brief (UOTGHS_SFR) B-Connection Error Interrupt Set */
+#define UOTGHS_SFR_ROLEEXIS (0x1u << 5) /**< \brief (UOTGHS_SFR) Role Exchange Interrupt Set */
+#define UOTGHS_SFR_HNPERRIS (0x1u << 6) /**< \brief (UOTGHS_SFR) HNP Error Interrupt Set */
+#define UOTGHS_SFR_STOIS (0x1u << 7) /**< \brief (UOTGHS_SFR) Suspend Time-Out Interrupt Set */
+#define UOTGHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (UOTGHS_SFR) VBus Request Set */
+/* -------- UOTGHS_FSM : (UOTGHS Offset: 0x082C) General Finite State Machine Register -------- */
+#define UOTGHS_FSM_DRDSTATE_Pos 0
+#define UOTGHS_FSM_DRDSTATE_Msk (0xfu << UOTGHS_FSM_DRDSTATE_Pos) /**< \brief (UOTGHS_FSM)  */
+#define   UOTGHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (UOTGHS_FSM) This is the start state for A-devices (when the ID pin is 0) */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */
+#define   UOTGHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device that operates in Host mode is operational. */
+#define   UOTGHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (UOTGHS_FSM) The A-device operating as a host is in the suspend mode. */
+#define   UOTGHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (UOTGHS_FSM) The A-device operates as a peripheral. */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */
+#define   UOTGHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */
+#define   UOTGHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (UOTGHS_FSM) This is the start state for B-device (when the ID pin is 1). */
+#define   UOTGHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the peripheral. */
+#define   UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */
+#define   UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. */
+#define   UOTGHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */
+#define   UOTGHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the Host. */
+#define   UOTGHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_UOTGHS_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_usart.h

@@ -0,0 +1,396 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART_COMPONENT_
+#define _SAM3XA_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+  RwReg US_LINMR;      /**< \brief (Usart Offset: 0x0054) LIN Mode Register */
+  RwReg US_LINIR;      /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */
+  RoReg Reserved3[34];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */
+#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN Master */
+#define   US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */
+#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */
+#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
+#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */
+#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */
+#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */
+#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */
+#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */
+#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */
+#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
+#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */
+#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */
+#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */
+#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */
+#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */
+#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */
+#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */
+#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */
+#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */
+#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */
+#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */
+#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */
+#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */
+#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */
+#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */
+#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */
+#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */
+#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */
+#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */
+#define US_LINMR_NACT_Pos 0
+#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */
+#define   US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */
+#define   US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */
+#define   US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */
+#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */
+#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */
+#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */
+#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */
+#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */
+#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */
+#define US_LINMR_DLC_Pos 8
+#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */
+#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
+#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) PDC Mode */
+/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */
+#define US_LINIR_IDCHR_Pos 0
+#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */
+#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_USART_COMPONENT_ */

lib/cmsis-sam3x8e/include/component/component_wdt.h

@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_WDT_COMPONENT_
+#define _SAM3XA_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_WDT Watchdog Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_WDT_COMPONENT_ */

lib/cmsis-sam3x8e/include/instance/instance_adc.h

@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_ADC_INSTANCE_
+#define _SAM3XA_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CR               (0x400C0000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR               (0x400C0004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1            (0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2            (0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER             (0x400C0010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR             (0x400C0014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR             (0x400C0018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR             (0x400C0020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER              (0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR              (0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR              (0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR              (0x400C0030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER             (0x400C003CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR              (0x400C0040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR              (0x400C0044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR              (0x400C0048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR              (0x400C004CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR              (0x400C0050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR              (0x400C0094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR             (0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR             (0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR              (0x400C0100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR              (0x400C0104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR             (0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR             (0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR             (0x400C0120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR             (0x400C0124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR      (*(WoReg*)0x400C0000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR      (*(RwReg*)0x400C0004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1   (*(RwReg*)0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2   (*(RwReg*)0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER    (*(WoReg*)0x400C0010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR    (*(WoReg*)0x400C0014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR    (*(RoReg*)0x400C0018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR    (*(RoReg*)0x400C0020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER     (*(WoReg*)0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR     (*(WoReg*)0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR     (*(RoReg*)0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR     (*(RoReg*)0x400C0030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER    (*(RoReg*)0x400C003CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR     (*(RwReg*)0x400C0040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR     (*(RwReg*)0x400C0044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR     (*(RwReg*)0x400C0048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR     (*(RwReg*)0x400C004CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR     (*(RoReg*)0x400C0050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR     (*(RwReg*)0x400C0094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR    (*(RwReg*)0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR    (*(RoReg*)0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR     (*(RwReg*)0x400C0100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR     (*(RwReg*)0x400C0104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR    (*(RwReg*)0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR    (*(RwReg*)0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR    (*(WoReg*)0x400C0120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR    (*(RoReg*)0x400C0124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_ADC_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_can0.h

@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CAN0_INSTANCE_
+#define _SAM3XA_CAN0_INSTANCE_
+
+/* ========== Register definition for CAN0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CAN0_MR               (0x400B4000U) /**< \brief (CAN0) Mode Register */
+#define REG_CAN0_IER              (0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */
+#define REG_CAN0_IDR              (0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */
+#define REG_CAN0_IMR              (0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */
+#define REG_CAN0_SR               (0x400B4010U) /**< \brief (CAN0) Status Register */
+#define REG_CAN0_BR               (0x400B4014U) /**< \brief (CAN0) Baudrate Register */
+#define REG_CAN0_TIM              (0x400B4018U) /**< \brief (CAN0) Timer Register */
+#define REG_CAN0_TIMESTP          (0x400B401CU) /**< \brief (CAN0) Timestamp Register */
+#define REG_CAN0_ECR              (0x400B4020U) /**< \brief (CAN0) Error Counter Register */
+#define REG_CAN0_TCR              (0x400B4024U) /**< \brief (CAN0) Transfer Command Register */
+#define REG_CAN0_ACR              (0x400B4028U) /**< \brief (CAN0) Abort Command Register */
+#define REG_CAN0_WPMR             (0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */
+#define REG_CAN0_WPSR             (0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */
+#define REG_CAN0_MMR0             (0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
+#define REG_CAN0_MAM0             (0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN0_MID0             (0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
+#define REG_CAN0_MFID0            (0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN0_MSR0             (0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
+#define REG_CAN0_MDL0             (0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN0_MDH0             (0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
+#define REG_CAN0_MCR0             (0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
+#define REG_CAN0_MMR1             (0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
+#define REG_CAN0_MAM1             (0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN0_MID1             (0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
+#define REG_CAN0_MFID1            (0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN0_MSR1             (0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
+#define REG_CAN0_MDL1             (0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN0_MDH1             (0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
+#define REG_CAN0_MCR1             (0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
+#define REG_CAN0_MMR2             (0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
+#define REG_CAN0_MAM2             (0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN0_MID2             (0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
+#define REG_CAN0_MFID2            (0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN0_MSR2             (0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
+#define REG_CAN0_MDL2             (0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN0_MDH2             (0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
+#define REG_CAN0_MCR2             (0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
+#define REG_CAN0_MMR3             (0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
+#define REG_CAN0_MAM3             (0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN0_MID3             (0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
+#define REG_CAN0_MFID3            (0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN0_MSR3             (0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
+#define REG_CAN0_MDL3             (0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN0_MDH3             (0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
+#define REG_CAN0_MCR3             (0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
+#define REG_CAN0_MMR4             (0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
+#define REG_CAN0_MAM4             (0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN0_MID4             (0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
+#define REG_CAN0_MFID4            (0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN0_MSR4             (0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
+#define REG_CAN0_MDL4             (0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN0_MDH4             (0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
+#define REG_CAN0_MCR4             (0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
+#define REG_CAN0_MMR5             (0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
+#define REG_CAN0_MAM5             (0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN0_MID5             (0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
+#define REG_CAN0_MFID5            (0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN0_MSR5             (0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
+#define REG_CAN0_MDL5             (0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN0_MDH5             (0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
+#define REG_CAN0_MCR5             (0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
+#define REG_CAN0_MMR6             (0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
+#define REG_CAN0_MAM6             (0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN0_MID6             (0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
+#define REG_CAN0_MFID6            (0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN0_MSR6             (0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
+#define REG_CAN0_MDL6             (0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN0_MDH6             (0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
+#define REG_CAN0_MCR6             (0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
+#define REG_CAN0_MMR7             (0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
+#define REG_CAN0_MAM7             (0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN0_MID7             (0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
+#define REG_CAN0_MFID7            (0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN0_MSR7             (0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
+#define REG_CAN0_MDL7             (0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN0_MDH7             (0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
+#define REG_CAN0_MCR7             (0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
+#else
+#define REG_CAN0_MR      (*(RwReg*)0x400B4000U) /**< \brief (CAN0) Mode Register */
+#define REG_CAN0_IER     (*(WoReg*)0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */
+#define REG_CAN0_IDR     (*(WoReg*)0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */
+#define REG_CAN0_IMR     (*(RoReg*)0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */
+#define REG_CAN0_SR      (*(RoReg*)0x400B4010U) /**< \brief (CAN0) Status Register */
+#define REG_CAN0_BR      (*(RwReg*)0x400B4014U) /**< \brief (CAN0) Baudrate Register */
+#define REG_CAN0_TIM     (*(RoReg*)0x400B4018U) /**< \brief (CAN0) Timer Register */
+#define REG_CAN0_TIMESTP (*(RoReg*)0x400B401CU) /**< \brief (CAN0) Timestamp Register */
+#define REG_CAN0_ECR     (*(RoReg*)0x400B4020U) /**< \brief (CAN0) Error Counter Register */
+#define REG_CAN0_TCR     (*(WoReg*)0x400B4024U) /**< \brief (CAN0) Transfer Command Register */
+#define REG_CAN0_ACR     (*(WoReg*)0x400B4028U) /**< \brief (CAN0) Abort Command Register */
+#define REG_CAN0_WPMR    (*(RwReg*)0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */
+#define REG_CAN0_WPSR    (*(RoReg*)0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */
+#define REG_CAN0_MMR0    (*(RwReg*)0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
+#define REG_CAN0_MAM0    (*(RwReg*)0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN0_MID0    (*(RwReg*)0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
+#define REG_CAN0_MFID0   (*(RoReg*)0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN0_MSR0    (*(RoReg*)0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
+#define REG_CAN0_MDL0    (*(RwReg*)0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN0_MDH0    (*(RwReg*)0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
+#define REG_CAN0_MCR0    (*(WoReg*)0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
+#define REG_CAN0_MMR1    (*(RwReg*)0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
+#define REG_CAN0_MAM1    (*(RwReg*)0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN0_MID1    (*(RwReg*)0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
+#define REG_CAN0_MFID1   (*(RoReg*)0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN0_MSR1    (*(RoReg*)0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
+#define REG_CAN0_MDL1    (*(RwReg*)0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN0_MDH1    (*(RwReg*)0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
+#define REG_CAN0_MCR1    (*(WoReg*)0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
+#define REG_CAN0_MMR2    (*(RwReg*)0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
+#define REG_CAN0_MAM2    (*(RwReg*)0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN0_MID2    (*(RwReg*)0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
+#define REG_CAN0_MFID2   (*(RoReg*)0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN0_MSR2    (*(RoReg*)0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
+#define REG_CAN0_MDL2    (*(RwReg*)0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN0_MDH2    (*(RwReg*)0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
+#define REG_CAN0_MCR2    (*(WoReg*)0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
+#define REG_CAN0_MMR3    (*(RwReg*)0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
+#define REG_CAN0_MAM3    (*(RwReg*)0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN0_MID3    (*(RwReg*)0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
+#define REG_CAN0_MFID3   (*(RoReg*)0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN0_MSR3    (*(RoReg*)0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
+#define REG_CAN0_MDL3    (*(RwReg*)0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN0_MDH3    (*(RwReg*)0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
+#define REG_CAN0_MCR3    (*(WoReg*)0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
+#define REG_CAN0_MMR4    (*(RwReg*)0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
+#define REG_CAN0_MAM4    (*(RwReg*)0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN0_MID4    (*(RwReg*)0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
+#define REG_CAN0_MFID4   (*(RoReg*)0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN0_MSR4    (*(RoReg*)0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
+#define REG_CAN0_MDL4    (*(RwReg*)0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN0_MDH4    (*(RwReg*)0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
+#define REG_CAN0_MCR4    (*(WoReg*)0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
+#define REG_CAN0_MMR5    (*(RwReg*)0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
+#define REG_CAN0_MAM5    (*(RwReg*)0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN0_MID5    (*(RwReg*)0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
+#define REG_CAN0_MFID5   (*(RoReg*)0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN0_MSR5    (*(RoReg*)0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
+#define REG_CAN0_MDL5    (*(RwReg*)0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN0_MDH5    (*(RwReg*)0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
+#define REG_CAN0_MCR5    (*(WoReg*)0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
+#define REG_CAN0_MMR6    (*(RwReg*)0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
+#define REG_CAN0_MAM6    (*(RwReg*)0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN0_MID6    (*(RwReg*)0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
+#define REG_CAN0_MFID6   (*(RoReg*)0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN0_MSR6    (*(RoReg*)0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
+#define REG_CAN0_MDL6    (*(RwReg*)0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN0_MDH6    (*(RwReg*)0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
+#define REG_CAN0_MCR6    (*(WoReg*)0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
+#define REG_CAN0_MMR7    (*(RwReg*)0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
+#define REG_CAN0_MAM7    (*(RwReg*)0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN0_MID7    (*(RwReg*)0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
+#define REG_CAN0_MFID7   (*(RoReg*)0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN0_MSR7    (*(RoReg*)0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
+#define REG_CAN0_MDL7    (*(RwReg*)0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN0_MDH7    (*(RwReg*)0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
+#define REG_CAN0_MCR7    (*(WoReg*)0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_CAN0_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_can1.h

@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CAN1_INSTANCE_
+#define _SAM3XA_CAN1_INSTANCE_
+
+/* ========== Register definition for CAN1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CAN1_MR               (0x400B8000U) /**< \brief (CAN1) Mode Register */
+#define REG_CAN1_IER              (0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */
+#define REG_CAN1_IDR              (0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */
+#define REG_CAN1_IMR              (0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */
+#define REG_CAN1_SR               (0x400B8010U) /**< \brief (CAN1) Status Register */
+#define REG_CAN1_BR               (0x400B8014U) /**< \brief (CAN1) Baudrate Register */
+#define REG_CAN1_TIM              (0x400B8018U) /**< \brief (CAN1) Timer Register */
+#define REG_CAN1_TIMESTP          (0x400B801CU) /**< \brief (CAN1) Timestamp Register */
+#define REG_CAN1_ECR              (0x400B8020U) /**< \brief (CAN1) Error Counter Register */
+#define REG_CAN1_TCR              (0x400B8024U) /**< \brief (CAN1) Transfer Command Register */
+#define REG_CAN1_ACR              (0x400B8028U) /**< \brief (CAN1) Abort Command Register */
+#define REG_CAN1_WPMR             (0x400B80E4U) /**< \brief (CAN1) Write Protect Mode Register */
+#define REG_CAN1_WPSR             (0x400B80E8U) /**< \brief (CAN1) Write Protect Status Register */
+#define REG_CAN1_MMR0             (0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
+#define REG_CAN1_MAM0             (0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN1_MID0             (0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
+#define REG_CAN1_MFID0            (0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN1_MSR0             (0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
+#define REG_CAN1_MDL0             (0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN1_MDH0             (0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
+#define REG_CAN1_MCR0             (0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
+#define REG_CAN1_MMR1             (0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
+#define REG_CAN1_MAM1             (0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN1_MID1             (0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
+#define REG_CAN1_MFID1            (0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN1_MSR1             (0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
+#define REG_CAN1_MDL1             (0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN1_MDH1             (0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
+#define REG_CAN1_MCR1             (0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
+#define REG_CAN1_MMR2             (0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
+#define REG_CAN1_MAM2             (0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN1_MID2             (0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
+#define REG_CAN1_MFID2            (0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN1_MSR2             (0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
+#define REG_CAN1_MDL2             (0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN1_MDH2             (0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
+#define REG_CAN1_MCR2             (0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
+#define REG_CAN1_MMR3             (0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
+#define REG_CAN1_MAM3             (0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN1_MID3             (0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
+#define REG_CAN1_MFID3            (0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN1_MSR3             (0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
+#define REG_CAN1_MDL3             (0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN1_MDH3             (0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
+#define REG_CAN1_MCR3             (0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
+#define REG_CAN1_MMR4             (0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
+#define REG_CAN1_MAM4             (0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN1_MID4             (0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
+#define REG_CAN1_MFID4            (0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN1_MSR4             (0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
+#define REG_CAN1_MDL4             (0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN1_MDH4             (0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
+#define REG_CAN1_MCR4             (0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
+#define REG_CAN1_MMR5             (0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
+#define REG_CAN1_MAM5             (0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN1_MID5             (0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
+#define REG_CAN1_MFID5            (0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN1_MSR5             (0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
+#define REG_CAN1_MDL5             (0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN1_MDH5             (0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
+#define REG_CAN1_MCR5             (0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
+#define REG_CAN1_MMR6             (0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
+#define REG_CAN1_MAM6             (0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN1_MID6             (0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
+#define REG_CAN1_MFID6            (0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN1_MSR6             (0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
+#define REG_CAN1_MDL6             (0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN1_MDH6             (0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
+#define REG_CAN1_MCR6             (0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
+#define REG_CAN1_MMR7             (0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
+#define REG_CAN1_MAM7             (0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN1_MID7             (0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
+#define REG_CAN1_MFID7            (0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN1_MSR7             (0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
+#define REG_CAN1_MDL7             (0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN1_MDH7             (0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
+#define REG_CAN1_MCR7             (0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
+#else
+#define REG_CAN1_MR      (*(RwReg*)0x400B8000U) /**< \brief (CAN1) Mode Register */
+#define REG_CAN1_IER     (*(WoReg*)0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */
+#define REG_CAN1_IDR     (*(WoReg*)0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */
+#define REG_CAN1_IMR     (*(RoReg*)0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */
+#define REG_CAN1_SR      (*(RoReg*)0x400B8010U) /**< \brief (CAN1) Status Register */
+#define REG_CAN1_BR      (*(RwReg*)0x400B8014U) /**< \brief (CAN1) Baudrate Register */
+#define REG_CAN1_TIM     (*(RoReg*)0x400B8018U) /**< \brief (CAN1) Timer Register */
+#define REG_CAN1_TIMESTP (*(RoReg*)0x400B801CU) /**< \brief (CAN1) Timestamp Register */
+#define REG_CAN1_ECR     (*(RoReg*)0x400B8020U) /**< \brief (CAN1) Error Counter Register */
+#define REG_CAN1_TCR     (*(WoReg*)0x400B8024U) /**< \brief (CAN1) Transfer Command Register */
+#define REG_CAN1_ACR     (*(WoReg*)0x400B8028U) /**< \brief (CAN1) Abort Command Register */
+#define REG_CAN1_WPMR    (*(RwReg*)0x400B80E4U) /**< \brief (CAN1) Write Protect Mode Register */
+#define REG_CAN1_WPSR    (*(RoReg*)0x400B80E8U) /**< \brief (CAN1) Write Protect Status Register */
+#define REG_CAN1_MMR0    (*(RwReg*)0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
+#define REG_CAN1_MAM0    (*(RwReg*)0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN1_MID0    (*(RwReg*)0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
+#define REG_CAN1_MFID0   (*(RoReg*)0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN1_MSR0    (*(RoReg*)0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
+#define REG_CAN1_MDL0    (*(RwReg*)0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN1_MDH0    (*(RwReg*)0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
+#define REG_CAN1_MCR0    (*(WoReg*)0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
+#define REG_CAN1_MMR1    (*(RwReg*)0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
+#define REG_CAN1_MAM1    (*(RwReg*)0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN1_MID1    (*(RwReg*)0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
+#define REG_CAN1_MFID1   (*(RoReg*)0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN1_MSR1    (*(RoReg*)0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
+#define REG_CAN1_MDL1    (*(RwReg*)0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN1_MDH1    (*(RwReg*)0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
+#define REG_CAN1_MCR1    (*(WoReg*)0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
+#define REG_CAN1_MMR2    (*(RwReg*)0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
+#define REG_CAN1_MAM2    (*(RwReg*)0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN1_MID2    (*(RwReg*)0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
+#define REG_CAN1_MFID2   (*(RoReg*)0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN1_MSR2    (*(RoReg*)0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
+#define REG_CAN1_MDL2    (*(RwReg*)0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN1_MDH2    (*(RwReg*)0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
+#define REG_CAN1_MCR2    (*(WoReg*)0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
+#define REG_CAN1_MMR3    (*(RwReg*)0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
+#define REG_CAN1_MAM3    (*(RwReg*)0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN1_MID3    (*(RwReg*)0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
+#define REG_CAN1_MFID3   (*(RoReg*)0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN1_MSR3    (*(RoReg*)0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
+#define REG_CAN1_MDL3    (*(RwReg*)0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN1_MDH3    (*(RwReg*)0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
+#define REG_CAN1_MCR3    (*(WoReg*)0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
+#define REG_CAN1_MMR4    (*(RwReg*)0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
+#define REG_CAN1_MAM4    (*(RwReg*)0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN1_MID4    (*(RwReg*)0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
+#define REG_CAN1_MFID4   (*(RoReg*)0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN1_MSR4    (*(RoReg*)0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
+#define REG_CAN1_MDL4    (*(RwReg*)0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN1_MDH4    (*(RwReg*)0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
+#define REG_CAN1_MCR4    (*(WoReg*)0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
+#define REG_CAN1_MMR5    (*(RwReg*)0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
+#define REG_CAN1_MAM5    (*(RwReg*)0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN1_MID5    (*(RwReg*)0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
+#define REG_CAN1_MFID5   (*(RoReg*)0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN1_MSR5    (*(RoReg*)0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
+#define REG_CAN1_MDL5    (*(RwReg*)0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN1_MDH5    (*(RwReg*)0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
+#define REG_CAN1_MCR5    (*(WoReg*)0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
+#define REG_CAN1_MMR6    (*(RwReg*)0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
+#define REG_CAN1_MAM6    (*(RwReg*)0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN1_MID6    (*(RwReg*)0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
+#define REG_CAN1_MFID6   (*(RoReg*)0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN1_MSR6    (*(RoReg*)0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
+#define REG_CAN1_MDL6    (*(RwReg*)0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN1_MDH6    (*(RwReg*)0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
+#define REG_CAN1_MCR6    (*(WoReg*)0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
+#define REG_CAN1_MMR7    (*(RwReg*)0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
+#define REG_CAN1_MAM7    (*(RwReg*)0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN1_MID7    (*(RwReg*)0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
+#define REG_CAN1_MFID7   (*(RoReg*)0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN1_MSR7    (*(RoReg*)0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
+#define REG_CAN1_MDL7    (*(RwReg*)0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN1_MDH7    (*(RwReg*)0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
+#define REG_CAN1_MCR7    (*(WoReg*)0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_CAN1_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_chipid.h

@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CHIPID_INSTANCE_
+#define _SAM3XA_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CHIPID_CIDR          (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_CHIPID_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_dacc.h

@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DACC_INSTANCE_
+#define _SAM3XA_DACC_INSTANCE_
+
+/* ========== Register definition for DACC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DACC_CR            (0x400C8000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR            (0x400C8004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER          (0x400C8010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR          (0x400C8014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR          (0x400C8018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR           (0x400C8020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER           (0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR           (0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR           (0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR           (0x400C8030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR           (0x400C8094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR          (0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR          (0x400C80E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_TPR           (0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR           (0x400C810CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR          (0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR          (0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR          (0x400C8120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR          (0x400C8124U) /**< \brief (DACC) Transfer Status Register */
+#else
+#define REG_DACC_CR   (*(WoReg*)0x400C8000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR   (*(RwReg*)0x400C8004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER (*(WoReg*)0x400C8010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR (*(WoReg*)0x400C8014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR (*(RoReg*)0x400C8018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR  (*(WoReg*)0x400C8020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER  (*(WoReg*)0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR  (*(WoReg*)0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR  (*(RoReg*)0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR  (*(RoReg*)0x400C8030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR  (*(RwReg*)0x400C8094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR (*(RwReg*)0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR (*(RoReg*)0x400C80E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_TPR  (*(RwReg*)0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR  (*(RwReg*)0x400C810CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR (*(RwReg*)0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR (*(RwReg*)0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR (*(WoReg*)0x400C8120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR (*(RoReg*)0x400C8124U) /**< \brief (DACC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_DACC_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_dmac.h

@@ -0,0 +1,138 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DMAC_INSTANCE_
+#define _SAM3XA_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_GCFG            (0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN              (0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ            (0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ            (0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST            (0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER          (0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR          (0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR          (0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR          (0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER            (0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR            (0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR            (0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0          (0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0          (0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0           (0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0          (0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0          (0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0            (0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1          (0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1          (0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1           (0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1          (0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1          (0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1            (0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2          (0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2          (0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2           (0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2          (0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2          (0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2            (0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3          (0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3          (0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3           (0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3          (0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3          (0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3            (0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#define REG_DMAC_SADDR4          (0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */
+#define REG_DMAC_DADDR4          (0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */
+#define REG_DMAC_DSCR4           (0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */
+#define REG_DMAC_CTRLA4          (0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */
+#define REG_DMAC_CTRLB4          (0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */
+#define REG_DMAC_CFG4            (0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */
+#define REG_DMAC_SADDR5          (0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */
+#define REG_DMAC_DADDR5          (0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */
+#define REG_DMAC_DSCR5           (0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */
+#define REG_DMAC_CTRLA5          (0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */
+#define REG_DMAC_CTRLB5          (0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */
+#define REG_DMAC_CFG5            (0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */
+#define REG_DMAC_WPMR            (0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
+#define REG_DMAC_WPSR            (0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
+#else
+#define REG_DMAC_GCFG   (*(RwReg*)0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN     (*(RwReg*)0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ   (*(RwReg*)0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ   (*(RwReg*)0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST   (*(RwReg*)0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER (*(WoReg*)0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR (*(WoReg*)0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR (*(RoReg*)0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR (*(RoReg*)0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER   (*(WoReg*)0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR   (*(WoReg*)0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR   (*(RoReg*)0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0 (*(RwReg*)0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0 (*(RwReg*)0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0  (*(RwReg*)0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0 (*(RwReg*)0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0 (*(RwReg*)0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0   (*(RwReg*)0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1 (*(RwReg*)0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1 (*(RwReg*)0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1  (*(RwReg*)0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1 (*(RwReg*)0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1 (*(RwReg*)0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1   (*(RwReg*)0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2 (*(RwReg*)0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2 (*(RwReg*)0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2  (*(RwReg*)0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2 (*(RwReg*)0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2 (*(RwReg*)0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2   (*(RwReg*)0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3 (*(RwReg*)0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3 (*(RwReg*)0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3  (*(RwReg*)0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3 (*(RwReg*)0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3 (*(RwReg*)0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3   (*(RwReg*)0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#define REG_DMAC_SADDR4 (*(RwReg*)0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */
+#define REG_DMAC_DADDR4 (*(RwReg*)0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */
+#define REG_DMAC_DSCR4  (*(RwReg*)0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */
+#define REG_DMAC_CTRLA4 (*(RwReg*)0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */
+#define REG_DMAC_CTRLB4 (*(RwReg*)0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */
+#define REG_DMAC_CFG4   (*(RwReg*)0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */
+#define REG_DMAC_SADDR5 (*(RwReg*)0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */
+#define REG_DMAC_DADDR5 (*(RwReg*)0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */
+#define REG_DMAC_DSCR5  (*(RwReg*)0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */
+#define REG_DMAC_CTRLA5 (*(RwReg*)0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */
+#define REG_DMAC_CTRLB5 (*(RwReg*)0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */
+#define REG_DMAC_CFG5   (*(RwReg*)0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */
+#define REG_DMAC_WPMR   (*(RwReg*)0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
+#define REG_DMAC_WPSR   (*(RoReg*)0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_DMAC_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_efc0.h

@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EFC0_INSTANCE_
+#define _SAM3XA_EFC0_INSTANCE_
+
+/* ========== Register definition for EFC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EFC0_FMR           (0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR           (0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR           (0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR           (0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */
+#else
+#define REG_EFC0_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_EFC0_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_efc1.h

@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EFC1_INSTANCE_
+#define _SAM3XA_EFC1_INSTANCE_
+
+/* ========== Register definition for EFC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EFC1_FMR           (0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR           (0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR           (0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR           (0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+#else
+#define REG_EFC1_FMR  (*(RwReg*)0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR  (*(WoReg*)0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR  (*(RoReg*)0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR  (*(RoReg*)0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_EFC1_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_emac.h

@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EMAC_INSTANCE_
+#define _SAM3XA_EMAC_INSTANCE_
+
+/* ========== Register definition for EMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EMAC_NCR            (0x400B0000U) /**< \brief (EMAC) Network Control Register */
+#define REG_EMAC_NCFGR          (0x400B0004U) /**< \brief (EMAC) Network Configuration Register */
+#define REG_EMAC_NSR            (0x400B0008U) /**< \brief (EMAC) Network Status Register */
+#define REG_EMAC_TSR            (0x400B0014U) /**< \brief (EMAC) Transmit Status Register */
+#define REG_EMAC_RBQP           (0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
+#define REG_EMAC_TBQP           (0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
+#define REG_EMAC_RSR            (0x400B0020U) /**< \brief (EMAC) Receive Status Register */
+#define REG_EMAC_ISR            (0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */
+#define REG_EMAC_IER            (0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */
+#define REG_EMAC_IDR            (0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */
+#define REG_EMAC_IMR            (0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */
+#define REG_EMAC_MAN            (0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */
+#define REG_EMAC_PTR            (0x400B0038U) /**< \brief (EMAC) Pause Time Register */
+#define REG_EMAC_PFR            (0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */
+#define REG_EMAC_FTO            (0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
+#define REG_EMAC_SCF            (0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */
+#define REG_EMAC_MCF            (0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */
+#define REG_EMAC_FRO            (0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */
+#define REG_EMAC_FCSE           (0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
+#define REG_EMAC_ALE            (0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */
+#define REG_EMAC_DTF            (0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
+#define REG_EMAC_LCOL           (0x400B005CU) /**< \brief (EMAC) Late Collisions Register */
+#define REG_EMAC_ECOL           (0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */
+#define REG_EMAC_TUND           (0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
+#define REG_EMAC_CSE            (0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */
+#define REG_EMAC_RRE            (0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */
+#define REG_EMAC_ROV            (0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */
+#define REG_EMAC_RSE            (0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */
+#define REG_EMAC_ELE            (0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */
+#define REG_EMAC_RJA            (0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */
+#define REG_EMAC_USF            (0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */
+#define REG_EMAC_STE            (0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */
+#define REG_EMAC_RLE            (0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
+#define REG_EMAC_HRB            (0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
+#define REG_EMAC_HRT            (0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
+#define REG_EMAC_SA1B           (0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
+#define REG_EMAC_SA1T           (0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */
+#define REG_EMAC_SA2B           (0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
+#define REG_EMAC_SA2T           (0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
+#define REG_EMAC_SA3B           (0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
+#define REG_EMAC_SA3T           (0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
+#define REG_EMAC_SA4B           (0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
+#define REG_EMAC_SA4T           (0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
+#define REG_EMAC_TID            (0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */
+#define REG_EMAC_USRIO          (0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */
+#else
+#define REG_EMAC_NCR   (*(RwReg*)0x400B0000U) /**< \brief (EMAC) Network Control Register */
+#define REG_EMAC_NCFGR (*(RwReg*)0x400B0004U) /**< \brief (EMAC) Network Configuration Register */
+#define REG_EMAC_NSR   (*(RoReg*)0x400B0008U) /**< \brief (EMAC) Network Status Register */
+#define REG_EMAC_TSR   (*(RwReg*)0x400B0014U) /**< \brief (EMAC) Transmit Status Register */
+#define REG_EMAC_RBQP  (*(RwReg*)0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
+#define REG_EMAC_TBQP  (*(RwReg*)0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
+#define REG_EMAC_RSR   (*(RwReg*)0x400B0020U) /**< \brief (EMAC) Receive Status Register */
+#define REG_EMAC_ISR   (*(RwReg*)0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */
+#define REG_EMAC_IER   (*(WoReg*)0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */
+#define REG_EMAC_IDR   (*(WoReg*)0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */
+#define REG_EMAC_IMR   (*(RoReg*)0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */
+#define REG_EMAC_MAN   (*(RwReg*)0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */
+#define REG_EMAC_PTR   (*(RwReg*)0x400B0038U) /**< \brief (EMAC) Pause Time Register */
+#define REG_EMAC_PFR   (*(RwReg*)0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */
+#define REG_EMAC_FTO   (*(RwReg*)0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
+#define REG_EMAC_SCF   (*(RwReg*)0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */
+#define REG_EMAC_MCF   (*(RwReg*)0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */
+#define REG_EMAC_FRO   (*(RwReg*)0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */
+#define REG_EMAC_FCSE  (*(RwReg*)0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
+#define REG_EMAC_ALE   (*(RwReg*)0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */
+#define REG_EMAC_DTF   (*(RwReg*)0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
+#define REG_EMAC_LCOL  (*(RwReg*)0x400B005CU) /**< \brief (EMAC) Late Collisions Register */
+#define REG_EMAC_ECOL  (*(RwReg*)0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */
+#define REG_EMAC_TUND  (*(RwReg*)0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
+#define REG_EMAC_CSE   (*(RwReg*)0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */
+#define REG_EMAC_RRE   (*(RwReg*)0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */
+#define REG_EMAC_ROV   (*(RwReg*)0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */
+#define REG_EMAC_RSE   (*(RwReg*)0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */
+#define REG_EMAC_ELE   (*(RwReg*)0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */
+#define REG_EMAC_RJA   (*(RwReg*)0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */
+#define REG_EMAC_USF   (*(RwReg*)0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */
+#define REG_EMAC_STE   (*(RwReg*)0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */
+#define REG_EMAC_RLE   (*(RwReg*)0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
+#define REG_EMAC_HRB   (*(RwReg*)0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
+#define REG_EMAC_HRT   (*(RwReg*)0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
+#define REG_EMAC_SA1B  (*(RwReg*)0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
+#define REG_EMAC_SA1T  (*(RwReg*)0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */
+#define REG_EMAC_SA2B  (*(RwReg*)0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
+#define REG_EMAC_SA2T  (*(RwReg*)0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
+#define REG_EMAC_SA3B  (*(RwReg*)0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
+#define REG_EMAC_SA3T  (*(RwReg*)0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
+#define REG_EMAC_SA4B  (*(RwReg*)0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
+#define REG_EMAC_SA4T  (*(RwReg*)0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
+#define REG_EMAC_TID   (*(RwReg*)0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */
+#define REG_EMAC_USRIO (*(RwReg*)0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_EMAC_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_gpbr.h

@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_GPBR_INSTANCE_
+#define _SAM3XA_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GPBR_GPBR            (0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_GPBR_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_hsmci.h

@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_HSMCI_INSTANCE_
+#define _SAM3XA_HSMCI_INSTANCE_
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_HSMCI_CR                 (0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR                 (0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR               (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR               (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR               (0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR               (0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR               (0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR              (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR               (0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR                (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR                (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR                 (0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER                (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR                (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR                (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA                (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG                (0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR               (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR               (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO               (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#else
+#define REG_HSMCI_CR        (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR        (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR      (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR      (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR      (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR      (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR      (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR     (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR      (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR       (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR       (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR        (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER       (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR       (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR       (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA       (*(RwReg*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG       (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR      (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR      (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO      (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_HSMCI_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_matrix.h

@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_MATRIX_INSTANCE_
+#define _SAM3XA_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MATRIX_MCFG             (0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG             (0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0            (0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1            (0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2            (0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3            (0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4            (0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5            (0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6            (0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7            (0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8            (0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_MRCR             (0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_CCFG_SYSIO              (0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR             (0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR             (0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG    (*(RwReg*)0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG    (*(RwReg*)0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0   (*(RwReg*)0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1   (*(RwReg*)0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2   (*(RwReg*)0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3   (*(RwReg*)0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4   (*(RwReg*)0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5   (*(RwReg*)0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6   (*(RwReg*)0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7   (*(RwReg*)0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8   (*(RwReg*)0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_MRCR    (*(RwReg*)0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_CCFG_SYSIO     (*(RwReg*)0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR    (*(RwReg*)0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR    (*(RoReg*)0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_MATRIX_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_pioa.h

@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOA_INSTANCE_
+#define _SAM3XA_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOA_PER             (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR             (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR             (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER             (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR             (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR             (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER            (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR            (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR            (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR            (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR            (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR            (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR            (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER             (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR             (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR             (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR             (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER            (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR            (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR            (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR            (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER            (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR            (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR            (0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR          (0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR           (0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR          (0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR            (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER            (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR            (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR            (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER           (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR           (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR           (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR             (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR             (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR            (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR          (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR          (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR          (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR          (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR            (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR            (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#else
+#define REG_PIOA_PER    (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR    (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR    (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER    (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR    (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR    (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER   (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR   (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR   (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR   (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR   (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR   (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR   (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER    (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR    (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR    (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR    (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER   (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR   (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR   (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR   (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER   (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR   (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR   (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR  (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR   (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER   (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR   (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR   (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER  (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR  (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR  (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR    (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR    (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR   (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR   (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR   (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOA_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_piob.h

@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOB_INSTANCE_
+#define _SAM3XA_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOB_PER             (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR             (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR             (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER             (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR             (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR             (0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER            (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR            (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR            (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR            (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR            (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR            (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR            (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER             (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR             (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR             (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR             (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER            (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR            (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR            (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR            (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER            (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR            (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR            (0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR          (0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR           (0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR          (0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR            (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER            (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR            (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR            (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER           (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR           (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR           (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR             (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR             (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR            (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR          (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR          (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR          (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR          (0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR            (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR            (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#else
+#define REG_PIOB_PER    (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR    (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR    (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER    (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR    (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR    (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER   (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR   (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR   (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR   (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR   (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR   (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR   (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER    (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR    (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR    (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR    (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER   (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR   (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR   (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR   (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER   (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR   (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR   (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR  (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR   (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER   (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR   (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR   (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER  (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR  (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR  (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR    (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR    (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR   (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR   (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR   (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOB_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_pioc.h

@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOC_INSTANCE_
+#define _SAM3XA_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOC_PER             (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR             (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR             (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER             (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR             (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR             (0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER            (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR            (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR            (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR            (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR            (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR            (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR            (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER             (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR             (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR             (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR             (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER            (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR            (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR            (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR            (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER            (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR            (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR            (0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR          (0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR           (0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR          (0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR            (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER            (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR            (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR            (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER           (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR           (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR           (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR             (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR             (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR            (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR          (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR          (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR          (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR          (0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR            (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR            (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#else
+#define REG_PIOC_PER    (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR    (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR    (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER    (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR    (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR    (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER   (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR   (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR   (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR   (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR   (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR   (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR   (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER    (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR    (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR    (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR    (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER   (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR   (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR   (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR   (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER   (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR   (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR   (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR  (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR   (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER   (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR   (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR   (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER  (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR  (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR  (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR    (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR    (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR   (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR   (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR   (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOC_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_piod.h

@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOD_INSTANCE_
+#define _SAM3XA_PIOD_INSTANCE_
+
+/* ========== Register definition for PIOD peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOD_PER             (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
+#define REG_PIOD_PDR             (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
+#define REG_PIOD_PSR             (0x400E1408U) /**< \brief (PIOD) PIO Status Register */
+#define REG_PIOD_OER             (0x400E1410U) /**< \brief (PIOD) Output Enable Register */
+#define REG_PIOD_ODR             (0x400E1414U) /**< \brief (PIOD) Output Disable Register */
+#define REG_PIOD_OSR             (0x400E1418U) /**< \brief (PIOD) Output Status Register */
+#define REG_PIOD_IFER            (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
+#define REG_PIOD_IFDR            (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
+#define REG_PIOD_IFSR            (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
+#define REG_PIOD_SODR            (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
+#define REG_PIOD_CODR            (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
+#define REG_PIOD_ODSR            (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
+#define REG_PIOD_PDSR            (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
+#define REG_PIOD_IER             (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
+#define REG_PIOD_IDR             (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
+#define REG_PIOD_IMR             (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
+#define REG_PIOD_ISR             (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
+#define REG_PIOD_MDER            (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
+#define REG_PIOD_MDDR            (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
+#define REG_PIOD_MDSR            (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
+#define REG_PIOD_PUDR            (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
+#define REG_PIOD_PUER            (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
+#define REG_PIOD_PUSR            (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
+#define REG_PIOD_ABSR            (0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */
+#define REG_PIOD_SCIFSR          (0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */
+#define REG_PIOD_DIFSR           (0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */
+#define REG_PIOD_IFDGSR          (0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOD_SCDR            (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
+#define REG_PIOD_OWER            (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
+#define REG_PIOD_OWDR            (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
+#define REG_PIOD_OWSR            (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
+#define REG_PIOD_AIMER           (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
+#define REG_PIOD_AIMDR           (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
+#define REG_PIOD_AIMMR           (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
+#define REG_PIOD_ESR             (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
+#define REG_PIOD_LSR             (0x400E14C4U) /**< \brief (PIOD) Level Select Register */
+#define REG_PIOD_ELSR            (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
+#define REG_PIOD_FELLSR          (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
+#define REG_PIOD_REHLSR          (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
+#define REG_PIOD_FRLHSR          (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
+#define REG_PIOD_LOCKSR          (0x400E14E0U) /**< \brief (PIOD) Lock Status */
+#define REG_PIOD_WPMR            (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
+#define REG_PIOD_WPSR            (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
+#else
+#define REG_PIOD_PER    (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
+#define REG_PIOD_PDR    (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
+#define REG_PIOD_PSR    (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */
+#define REG_PIOD_OER    (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */
+#define REG_PIOD_ODR    (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */
+#define REG_PIOD_OSR    (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */
+#define REG_PIOD_IFER   (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
+#define REG_PIOD_IFDR   (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
+#define REG_PIOD_IFSR   (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
+#define REG_PIOD_SODR   (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
+#define REG_PIOD_CODR   (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
+#define REG_PIOD_ODSR   (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
+#define REG_PIOD_PDSR   (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
+#define REG_PIOD_IER    (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
+#define REG_PIOD_IDR    (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
+#define REG_PIOD_IMR    (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
+#define REG_PIOD_ISR    (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
+#define REG_PIOD_MDER   (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
+#define REG_PIOD_MDDR   (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
+#define REG_PIOD_MDSR   (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
+#define REG_PIOD_PUDR   (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
+#define REG_PIOD_PUER   (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
+#define REG_PIOD_PUSR   (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
+#define REG_PIOD_ABSR   (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */
+#define REG_PIOD_SCIFSR (*(WoReg*)0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */
+#define REG_PIOD_DIFSR  (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */
+#define REG_PIOD_IFDGSR (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOD_SCDR   (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
+#define REG_PIOD_OWER   (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
+#define REG_PIOD_OWDR   (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
+#define REG_PIOD_OWSR   (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
+#define REG_PIOD_AIMER  (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
+#define REG_PIOD_AIMDR  (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
+#define REG_PIOD_AIMMR  (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
+#define REG_PIOD_ESR    (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
+#define REG_PIOD_LSR    (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */
+#define REG_PIOD_ELSR   (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
+#define REG_PIOD_FELLSR (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
+#define REG_PIOD_REHLSR (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
+#define REG_PIOD_FRLHSR (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
+#define REG_PIOD_LOCKSR (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */
+#define REG_PIOD_WPMR   (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
+#define REG_PIOD_WPSR   (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOD_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_pioe.h

@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOE_INSTANCE_
+#define _SAM3XA_PIOE_INSTANCE_
+
+/* ========== Register definition for PIOE peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOE_PER             (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
+#define REG_PIOE_PDR             (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
+#define REG_PIOE_PSR             (0x400E1608U) /**< \brief (PIOE) PIO Status Register */
+#define REG_PIOE_OER             (0x400E1610U) /**< \brief (PIOE) Output Enable Register */
+#define REG_PIOE_ODR             (0x400E1614U) /**< \brief (PIOE) Output Disable Register */
+#define REG_PIOE_OSR             (0x400E1618U) /**< \brief (PIOE) Output Status Register */
+#define REG_PIOE_IFER            (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
+#define REG_PIOE_IFDR            (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
+#define REG_PIOE_IFSR            (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
+#define REG_PIOE_SODR            (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
+#define REG_PIOE_CODR            (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
+#define REG_PIOE_ODSR            (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
+#define REG_PIOE_PDSR            (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
+#define REG_PIOE_IER             (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
+#define REG_PIOE_IDR             (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
+#define REG_PIOE_IMR             (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
+#define REG_PIOE_ISR             (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
+#define REG_PIOE_MDER            (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
+#define REG_PIOE_MDDR            (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
+#define REG_PIOE_MDSR            (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
+#define REG_PIOE_PUDR            (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
+#define REG_PIOE_PUER            (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
+#define REG_PIOE_PUSR            (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
+#define REG_PIOE_ABSR            (0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */
+#define REG_PIOE_SCIFSR          (0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */
+#define REG_PIOE_DIFSR           (0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */
+#define REG_PIOE_IFDGSR          (0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOE_SCDR            (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
+#define REG_PIOE_OWER            (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
+#define REG_PIOE_OWDR            (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
+#define REG_PIOE_OWSR            (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
+#define REG_PIOE_AIMER           (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
+#define REG_PIOE_AIMDR           (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
+#define REG_PIOE_AIMMR           (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
+#define REG_PIOE_ESR             (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
+#define REG_PIOE_LSR             (0x400E16C4U) /**< \brief (PIOE) Level Select Register */
+#define REG_PIOE_ELSR            (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
+#define REG_PIOE_FELLSR          (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
+#define REG_PIOE_REHLSR          (0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
+#define REG_PIOE_FRLHSR          (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
+#define REG_PIOE_LOCKSR          (0x400E16E0U) /**< \brief (PIOE) Lock Status */
+#define REG_PIOE_WPMR            (0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */
+#define REG_PIOE_WPSR            (0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */
+#else
+#define REG_PIOE_PER    (*(WoReg*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
+#define REG_PIOE_PDR    (*(WoReg*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
+#define REG_PIOE_PSR    (*(RoReg*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */
+#define REG_PIOE_OER    (*(WoReg*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */
+#define REG_PIOE_ODR    (*(WoReg*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */
+#define REG_PIOE_OSR    (*(RoReg*)0x400E1618U) /**< \brief (PIOE) Output Status Register */
+#define REG_PIOE_IFER   (*(WoReg*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
+#define REG_PIOE_IFDR   (*(WoReg*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
+#define REG_PIOE_IFSR   (*(RoReg*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
+#define REG_PIOE_SODR   (*(WoReg*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
+#define REG_PIOE_CODR   (*(WoReg*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
+#define REG_PIOE_ODSR   (*(RwReg*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
+#define REG_PIOE_PDSR   (*(RoReg*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
+#define REG_PIOE_IER    (*(WoReg*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
+#define REG_PIOE_IDR    (*(WoReg*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
+#define REG_PIOE_IMR    (*(RoReg*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
+#define REG_PIOE_ISR    (*(RoReg*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
+#define REG_PIOE_MDER   (*(WoReg*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
+#define REG_PIOE_MDDR   (*(WoReg*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
+#define REG_PIOE_MDSR   (*(RoReg*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
+#define REG_PIOE_PUDR   (*(WoReg*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
+#define REG_PIOE_PUER   (*(WoReg*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
+#define REG_PIOE_PUSR   (*(RoReg*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
+#define REG_PIOE_ABSR   (*(RwReg*)0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */
+#define REG_PIOE_SCIFSR (*(WoReg*)0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */
+#define REG_PIOE_DIFSR  (*(WoReg*)0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */
+#define REG_PIOE_IFDGSR (*(RoReg*)0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOE_SCDR   (*(RwReg*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
+#define REG_PIOE_OWER   (*(WoReg*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
+#define REG_PIOE_OWDR   (*(WoReg*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
+#define REG_PIOE_OWSR   (*(RoReg*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
+#define REG_PIOE_AIMER  (*(WoReg*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
+#define REG_PIOE_AIMDR  (*(WoReg*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
+#define REG_PIOE_AIMMR  (*(RoReg*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
+#define REG_PIOE_ESR    (*(WoReg*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
+#define REG_PIOE_LSR    (*(WoReg*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */
+#define REG_PIOE_ELSR   (*(RoReg*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
+#define REG_PIOE_FELLSR (*(WoReg*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
+#define REG_PIOE_REHLSR (*(WoReg*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
+#define REG_PIOE_FRLHSR (*(RoReg*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
+#define REG_PIOE_LOCKSR (*(RoReg*)0x400E16E0U) /**< \brief (PIOE) Lock Status */
+#define REG_PIOE_WPMR   (*(RwReg*)0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */
+#define REG_PIOE_WPSR   (*(RoReg*)0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOE_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_piof.h

@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOF_INSTANCE_
+#define _SAM3XA_PIOF_INSTANCE_
+
+/* ========== Register definition for PIOF peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOF_PER             (0x400E1800U) /**< \brief (PIOF) PIO Enable Register */
+#define REG_PIOF_PDR             (0x400E1804U) /**< \brief (PIOF) PIO Disable Register */
+#define REG_PIOF_PSR             (0x400E1808U) /**< \brief (PIOF) PIO Status Register */
+#define REG_PIOF_OER             (0x400E1810U) /**< \brief (PIOF) Output Enable Register */
+#define REG_PIOF_ODR             (0x400E1814U) /**< \brief (PIOF) Output Disable Register */
+#define REG_PIOF_OSR             (0x400E1818U) /**< \brief (PIOF) Output Status Register */
+#define REG_PIOF_IFER            (0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */
+#define REG_PIOF_IFDR            (0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */
+#define REG_PIOF_IFSR            (0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */
+#define REG_PIOF_SODR            (0x400E1830U) /**< \brief (PIOF) Set Output Data Register */
+#define REG_PIOF_CODR            (0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */
+#define REG_PIOF_ODSR            (0x400E1838U) /**< \brief (PIOF) Output Data Status Register */
+#define REG_PIOF_PDSR            (0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */
+#define REG_PIOF_IER             (0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */
+#define REG_PIOF_IDR             (0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */
+#define REG_PIOF_IMR             (0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */
+#define REG_PIOF_ISR             (0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */
+#define REG_PIOF_MDER            (0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */
+#define REG_PIOF_MDDR            (0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */
+#define REG_PIOF_MDSR            (0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */
+#define REG_PIOF_PUDR            (0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */
+#define REG_PIOF_PUER            (0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */
+#define REG_PIOF_PUSR            (0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */
+#define REG_PIOF_ABSR            (0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */
+#define REG_PIOF_SCIFSR          (0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */
+#define REG_PIOF_DIFSR           (0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */
+#define REG_PIOF_IFDGSR          (0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOF_SCDR            (0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */
+#define REG_PIOF_OWER            (0x400E18A0U) /**< \brief (PIOF) Output Write Enable */
+#define REG_PIOF_OWDR            (0x400E18A4U) /**< \brief (PIOF) Output Write Disable */
+#define REG_PIOF_OWSR            (0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */
+#define REG_PIOF_AIMER           (0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */
+#define REG_PIOF_AIMDR           (0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */
+#define REG_PIOF_AIMMR           (0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */
+#define REG_PIOF_ESR             (0x400E18C0U) /**< \brief (PIOF) Edge Select Register */
+#define REG_PIOF_LSR             (0x400E18C4U) /**< \brief (PIOF) Level Select Register */
+#define REG_PIOF_ELSR            (0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */
+#define REG_PIOF_FELLSR          (0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */
+#define REG_PIOF_REHLSR          (0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */
+#define REG_PIOF_FRLHSR          (0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */
+#define REG_PIOF_LOCKSR          (0x400E18E0U) /**< \brief (PIOF) Lock Status */
+#define REG_PIOF_WPMR            (0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */
+#define REG_PIOF_WPSR            (0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */
+#else
+#define REG_PIOF_PER    (*(WoReg*)0x400E1800U) /**< \brief (PIOF) PIO Enable Register */
+#define REG_PIOF_PDR    (*(WoReg*)0x400E1804U) /**< \brief (PIOF) PIO Disable Register */
+#define REG_PIOF_PSR    (*(RoReg*)0x400E1808U) /**< \brief (PIOF) PIO Status Register */
+#define REG_PIOF_OER    (*(WoReg*)0x400E1810U) /**< \brief (PIOF) Output Enable Register */
+#define REG_PIOF_ODR    (*(WoReg*)0x400E1814U) /**< \brief (PIOF) Output Disable Register */
+#define REG_PIOF_OSR    (*(RoReg*)0x400E1818U) /**< \brief (PIOF) Output Status Register */
+#define REG_PIOF_IFER   (*(WoReg*)0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */
+#define REG_PIOF_IFDR   (*(WoReg*)0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */
+#define REG_PIOF_IFSR   (*(RoReg*)0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */
+#define REG_PIOF_SODR   (*(WoReg*)0x400E1830U) /**< \brief (PIOF) Set Output Data Register */
+#define REG_PIOF_CODR   (*(WoReg*)0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */
+#define REG_PIOF_ODSR   (*(RwReg*)0x400E1838U) /**< \brief (PIOF) Output Data Status Register */
+#define REG_PIOF_PDSR   (*(RoReg*)0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */
+#define REG_PIOF_IER    (*(WoReg*)0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */
+#define REG_PIOF_IDR    (*(WoReg*)0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */
+#define REG_PIOF_IMR    (*(RoReg*)0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */
+#define REG_PIOF_ISR    (*(RoReg*)0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */
+#define REG_PIOF_MDER   (*(WoReg*)0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */
+#define REG_PIOF_MDDR   (*(WoReg*)0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */
+#define REG_PIOF_MDSR   (*(RoReg*)0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */
+#define REG_PIOF_PUDR   (*(WoReg*)0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */
+#define REG_PIOF_PUER   (*(WoReg*)0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */
+#define REG_PIOF_PUSR   (*(RoReg*)0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */
+#define REG_PIOF_ABSR   (*(RwReg*)0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */
+#define REG_PIOF_SCIFSR (*(WoReg*)0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */
+#define REG_PIOF_DIFSR  (*(WoReg*)0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */
+#define REG_PIOF_IFDGSR (*(RoReg*)0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOF_SCDR   (*(RwReg*)0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */
+#define REG_PIOF_OWER   (*(WoReg*)0x400E18A0U) /**< \brief (PIOF) Output Write Enable */
+#define REG_PIOF_OWDR   (*(WoReg*)0x400E18A4U) /**< \brief (PIOF) Output Write Disable */
+#define REG_PIOF_OWSR   (*(RoReg*)0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */
+#define REG_PIOF_AIMER  (*(WoReg*)0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */
+#define REG_PIOF_AIMDR  (*(WoReg*)0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */
+#define REG_PIOF_AIMMR  (*(RoReg*)0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */
+#define REG_PIOF_ESR    (*(WoReg*)0x400E18C0U) /**< \brief (PIOF) Edge Select Register */
+#define REG_PIOF_LSR    (*(WoReg*)0x400E18C4U) /**< \brief (PIOF) Level Select Register */
+#define REG_PIOF_ELSR   (*(RoReg*)0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */
+#define REG_PIOF_FELLSR (*(WoReg*)0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */
+#define REG_PIOF_REHLSR (*(WoReg*)0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */
+#define REG_PIOF_FRLHSR (*(RoReg*)0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */
+#define REG_PIOF_LOCKSR (*(RoReg*)0x400E18E0U) /**< \brief (PIOF) Lock Status */
+#define REG_PIOF_WPMR   (*(RwReg*)0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */
+#define REG_PIOF_WPSR   (*(RoReg*)0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOF_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_pmc.h

@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PMC_INSTANCE_
+#define _SAM3XA_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PMC_SCER            (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0608U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR           (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR            (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0628U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR            (0x400E0630U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB             (0x400E0638U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK             (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0668U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1           (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1           (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1           (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_PCR             (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR  (*(RwReg*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RoReg*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0628U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0630U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB    (*(RwReg*)0x400E0638U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0668U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1  (*(WoReg*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1  (*(WoReg*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1  (*(RoReg*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_PCR    (*(RwReg*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PMC_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_pwm.h

@@ -0,0 +1,306 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PWM_INSTANCE_
+#define _SAM3XA_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PWM_CLK               (0x40094000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA               (0x40094004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS               (0x40094008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR                (0x4009400CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1              (0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1              (0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1              (0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1              (0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM               (0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC              (0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP              (0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD           (0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2              (0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2              (0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2              (0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2              (0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV               (0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS                (0x40094048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS               (0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC               (0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD            (0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD            (0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR               (0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR               (0x40094060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR               (0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV               (0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE1              (0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */
+#define REG_PWM_FPE2              (0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */
+#define REG_PWM_ELMR              (0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR              (0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR              (0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR              (0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR               (0x40094108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR               (0x4009410CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR              (0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR              (0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR              (0x40094120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR              (0x40094124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0             (0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0          (0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0             (0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0          (0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1             (0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1          (0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1             (0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1          (0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2             (0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2          (0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2             (0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2          (0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3             (0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3          (0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3             (0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3          (0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4             (0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4          (0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4             (0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4          (0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5             (0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5          (0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5             (0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5          (0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6             (0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6          (0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6             (0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6          (0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7             (0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7          (0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7             (0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7          (0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0              (0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0             (0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0          (0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0             (0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0          (0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0             (0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0               (0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0            (0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1              (0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1             (0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1          (0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1             (0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1          (0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1             (0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1               (0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1            (0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2              (0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2             (0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2          (0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2             (0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2          (0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2             (0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2               (0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2            (0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3              (0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3             (0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3          (0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3             (0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3          (0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3             (0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3               (0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3            (0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#define REG_PWM_CMR4              (0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */
+#define REG_PWM_CDTY4             (0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */
+#define REG_PWM_CDTYUPD4          (0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */
+#define REG_PWM_CPRD4             (0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */
+#define REG_PWM_CPRDUPD4          (0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */
+#define REG_PWM_CCNT4             (0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */
+#define REG_PWM_DT4               (0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */
+#define REG_PWM_DTUPD4            (0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */
+#define REG_PWM_CMR5              (0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */
+#define REG_PWM_CDTY5             (0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */
+#define REG_PWM_CDTYUPD5          (0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */
+#define REG_PWM_CPRD5             (0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */
+#define REG_PWM_CPRDUPD5          (0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */
+#define REG_PWM_CCNT5             (0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */
+#define REG_PWM_DT5               (0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */
+#define REG_PWM_DTUPD5            (0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */
+#define REG_PWM_CMR6              (0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */
+#define REG_PWM_CDTY6             (0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */
+#define REG_PWM_CDTYUPD6          (0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */
+#define REG_PWM_CPRD6             (0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */
+#define REG_PWM_CPRDUPD6          (0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */
+#define REG_PWM_CCNT6             (0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */
+#define REG_PWM_DT6               (0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */
+#define REG_PWM_DTUPD6            (0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */
+#define REG_PWM_CMR7              (0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */
+#define REG_PWM_CDTY7             (0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */
+#define REG_PWM_CDTYUPD7          (0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */
+#define REG_PWM_CPRD7             (0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */
+#define REG_PWM_CPRDUPD7          (0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */
+#define REG_PWM_CCNT7             (0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */
+#define REG_PWM_DT7               (0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */
+#define REG_PWM_DTUPD7            (0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */
+#else
+#define REG_PWM_CLK      (*(RwReg*)0x40094000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA      (*(WoReg*)0x40094004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS      (*(WoReg*)0x40094008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR       (*(RoReg*)0x4009400CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1     (*(WoReg*)0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1     (*(WoReg*)0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1     (*(RoReg*)0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1     (*(RoReg*)0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM      (*(RwReg*)0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC     (*(RwReg*)0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP     (*(RwReg*)0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD  (*(WoReg*)0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2     (*(WoReg*)0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2     (*(WoReg*)0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2     (*(RoReg*)0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2     (*(RoReg*)0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV      (*(RwReg*)0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS       (*(RwReg*)0x40094048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS      (*(WoReg*)0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC      (*(WoReg*)0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD   (*(WoReg*)0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD   (*(WoReg*)0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR      (*(RwReg*)0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR      (*(RoReg*)0x40094060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR      (*(WoReg*)0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV      (*(RwReg*)0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE1     (*(RwReg*)0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */
+#define REG_PWM_FPE2     (*(RwReg*)0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */
+#define REG_PWM_ELMR     (*(RwReg*)0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR     (*(RwReg*)0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR     (*(WoReg*)0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR     (*(RoReg*)0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR      (*(RwReg*)0x40094108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR      (*(RwReg*)0x4009410CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR     (*(RwReg*)0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR     (*(RwReg*)0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR     (*(WoReg*)0x40094120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR     (*(RoReg*)0x40094124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0    (*(RwReg*)0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0    (*(RwReg*)0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1    (*(RwReg*)0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1    (*(RwReg*)0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2    (*(RwReg*)0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2    (*(RwReg*)0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3    (*(RwReg*)0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3    (*(RwReg*)0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4    (*(RwReg*)0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4    (*(RwReg*)0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5    (*(RwReg*)0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5    (*(RwReg*)0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6    (*(RwReg*)0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6    (*(RwReg*)0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7    (*(RwReg*)0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7    (*(RwReg*)0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0     (*(RwReg*)0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0    (*(RwReg*)0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0    (*(RwReg*)0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0    (*(RoReg*)0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0      (*(RwReg*)0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0   (*(WoReg*)0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1     (*(RwReg*)0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1    (*(RwReg*)0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1    (*(RwReg*)0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1    (*(RoReg*)0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1      (*(RwReg*)0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1   (*(WoReg*)0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2     (*(RwReg*)0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2    (*(RwReg*)0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2    (*(RwReg*)0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2    (*(RoReg*)0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2      (*(RwReg*)0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2   (*(WoReg*)0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3     (*(RwReg*)0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3    (*(RwReg*)0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3    (*(RwReg*)0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3    (*(RoReg*)0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3      (*(RwReg*)0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3   (*(WoReg*)0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#define REG_PWM_CMR4     (*(RwReg*)0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */
+#define REG_PWM_CDTY4    (*(RwReg*)0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */
+#define REG_PWM_CDTYUPD4 (*(WoReg*)0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */
+#define REG_PWM_CPRD4    (*(RwReg*)0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */
+#define REG_PWM_CPRDUPD4 (*(WoReg*)0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */
+#define REG_PWM_CCNT4    (*(RoReg*)0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */
+#define REG_PWM_DT4      (*(RwReg*)0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */
+#define REG_PWM_DTUPD4   (*(WoReg*)0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */
+#define REG_PWM_CMR5     (*(RwReg*)0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */
+#define REG_PWM_CDTY5    (*(RwReg*)0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */
+#define REG_PWM_CDTYUPD5 (*(WoReg*)0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */
+#define REG_PWM_CPRD5    (*(RwReg*)0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */
+#define REG_PWM_CPRDUPD5 (*(WoReg*)0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */
+#define REG_PWM_CCNT5    (*(RoReg*)0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */
+#define REG_PWM_DT5      (*(RwReg*)0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */
+#define REG_PWM_DTUPD5   (*(WoReg*)0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */
+#define REG_PWM_CMR6     (*(RwReg*)0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */
+#define REG_PWM_CDTY6    (*(RwReg*)0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */
+#define REG_PWM_CDTYUPD6 (*(WoReg*)0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */
+#define REG_PWM_CPRD6    (*(RwReg*)0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */
+#define REG_PWM_CPRDUPD6 (*(WoReg*)0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */
+#define REG_PWM_CCNT6    (*(RoReg*)0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */
+#define REG_PWM_DT6      (*(RwReg*)0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */
+#define REG_PWM_DTUPD6   (*(WoReg*)0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */
+#define REG_PWM_CMR7     (*(RwReg*)0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */
+#define REG_PWM_CDTY7    (*(RwReg*)0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */
+#define REG_PWM_CDTYUPD7 (*(WoReg*)0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */
+#define REG_PWM_CPRD7    (*(RwReg*)0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */
+#define REG_PWM_CPRDUPD7 (*(WoReg*)0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */
+#define REG_PWM_CCNT7    (*(RoReg*)0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */
+#define REG_PWM_DT7      (*(RwReg*)0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */
+#define REG_PWM_DTUPD7   (*(WoReg*)0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PWM_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_rstc.h

@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RSTC_INSTANCE_
+#define _SAM3XA_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RSTC_CR          (0x400E1A00U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1A04U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1A08U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1A00U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1A04U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1A08U) /**< \brief (RSTC) Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_RSTC_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_rtc.h

@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTC_INSTANCE_
+#define _SAM3XA_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_CR              (0x400E1A60U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1A64U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1A68U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E1A6CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1A70U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1A78U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR            (0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1A60U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1A64U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1A68U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E1A6CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1A70U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1A78U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR   (*(RwReg*)0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_RTC_INSTANCE_ */

lib/cmsis-sam3x8e/include/instance/instance_rtt.h

@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTT_INSTANCE_
+#define _SAM3XA_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTT_MR          (0x400E1A30U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1A34U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1A38U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E1A3CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1A30U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1A34U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1A38U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E1A3CU) /**< \brief (RTT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_RTT_INSTANCE_ */