110 lines
7.3 KiB
C
110 lines
7.3 KiB
C
/**
|
|
* \file
|
|
*
|
|
* \brief Instance description for TC2
|
|
*
|
|
* Copyright (c) 2018 Microchip Technology Inc.
|
|
*
|
|
* \asf_license_start
|
|
*
|
|
* \page License
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
|
* not use this file except in compliance with the License.
|
|
* You may obtain a copy of the Licence at
|
|
*
|
|
* http://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* \asf_license_stop
|
|
*
|
|
*/
|
|
|
|
#ifndef _SAMC21_TC2_INSTANCE_
|
|
#define _SAMC21_TC2_INSTANCE_
|
|
|
|
/* ========== Register definition for TC2 peripheral ========== */
|
|
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
|
#define REG_TC2_CTRLA (0x42003800) /**< \brief (TC2) Control A */
|
|
#define REG_TC2_CTRLBCLR (0x42003804) /**< \brief (TC2) Control B Clear */
|
|
#define REG_TC2_CTRLBSET (0x42003805) /**< \brief (TC2) Control B Set */
|
|
#define REG_TC2_EVCTRL (0x42003806) /**< \brief (TC2) Event Control */
|
|
#define REG_TC2_INTENCLR (0x42003808) /**< \brief (TC2) Interrupt Enable Clear */
|
|
#define REG_TC2_INTENSET (0x42003809) /**< \brief (TC2) Interrupt Enable Set */
|
|
#define REG_TC2_INTFLAG (0x4200380A) /**< \brief (TC2) Interrupt Flag Status and Clear */
|
|
#define REG_TC2_STATUS (0x4200380B) /**< \brief (TC2) Status */
|
|
#define REG_TC2_WAVE (0x4200380C) /**< \brief (TC2) Waveform Generation Control */
|
|
#define REG_TC2_DRVCTRL (0x4200380D) /**< \brief (TC2) Control C */
|
|
#define REG_TC2_DBGCTRL (0x4200380F) /**< \brief (TC2) Debug Control */
|
|
#define REG_TC2_SYNCBUSY (0x42003810) /**< \brief (TC2) Synchronization Status */
|
|
#define REG_TC2_COUNT16_COUNT (0x42003814) /**< \brief (TC2) COUNT16 Count */
|
|
#define REG_TC2_COUNT16_CC0 (0x4200381C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
|
|
#define REG_TC2_COUNT16_CC1 (0x4200381E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
|
|
#define REG_TC2_COUNT16_CCBUF0 (0x42003830) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
|
|
#define REG_TC2_COUNT16_CCBUF1 (0x42003832) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
|
|
#define REG_TC2_COUNT32_COUNT (0x42003814) /**< \brief (TC2) COUNT32 Count */
|
|
#define REG_TC2_COUNT32_CC0 (0x4200381C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
|
|
#define REG_TC2_COUNT32_CC1 (0x42003820) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
|
|
#define REG_TC2_COUNT32_CCBUF0 (0x42003830) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
|
|
#define REG_TC2_COUNT32_CCBUF1 (0x42003834) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
|
|
#define REG_TC2_COUNT8_COUNT (0x42003814) /**< \brief (TC2) COUNT8 Count */
|
|
#define REG_TC2_COUNT8_PER (0x4200381B) /**< \brief (TC2) COUNT8 Period */
|
|
#define REG_TC2_COUNT8_CC0 (0x4200381C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
|
|
#define REG_TC2_COUNT8_CC1 (0x4200381D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
|
|
#define REG_TC2_COUNT8_PERBUF (0x4200382F) /**< \brief (TC2) COUNT8 Period Buffer */
|
|
#define REG_TC2_COUNT8_CCBUF0 (0x42003830) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
|
|
#define REG_TC2_COUNT8_CCBUF1 (0x42003831) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
|
|
#else
|
|
#define REG_TC2_CTRLA (*(RwReg *)0x42003800UL) /**< \brief (TC2) Control A */
|
|
#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42003804UL) /**< \brief (TC2) Control B Clear */
|
|
#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42003805UL) /**< \brief (TC2) Control B Set */
|
|
#define REG_TC2_EVCTRL (*(RwReg16*)0x42003806UL) /**< \brief (TC2) Event Control */
|
|
#define REG_TC2_INTENCLR (*(RwReg8 *)0x42003808UL) /**< \brief (TC2) Interrupt Enable Clear */
|
|
#define REG_TC2_INTENSET (*(RwReg8 *)0x42003809UL) /**< \brief (TC2) Interrupt Enable Set */
|
|
#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200380AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */
|
|
#define REG_TC2_STATUS (*(RwReg8 *)0x4200380BUL) /**< \brief (TC2) Status */
|
|
#define REG_TC2_WAVE (*(RwReg8 *)0x4200380CUL) /**< \brief (TC2) Waveform Generation Control */
|
|
#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200380DUL) /**< \brief (TC2) Control C */
|
|
#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200380FUL) /**< \brief (TC2) Debug Control */
|
|
#define REG_TC2_SYNCBUSY (*(RoReg *)0x42003810UL) /**< \brief (TC2) Synchronization Status */
|
|
#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42003814UL) /**< \brief (TC2) COUNT16 Count */
|
|
#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200381CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
|
|
#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200381EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
|
|
#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42003830UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
|
|
#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42003832UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
|
|
#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42003814UL) /**< \brief (TC2) COUNT32 Count */
|
|
#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200381CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
|
|
#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42003820UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
|
|
#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42003830UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
|
|
#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42003834UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
|
|
#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42003814UL) /**< \brief (TC2) COUNT8 Count */
|
|
#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200381BUL) /**< \brief (TC2) COUNT8 Period */
|
|
#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200381CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
|
|
#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200381DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
|
|
#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200382FUL) /**< \brief (TC2) COUNT8 Period Buffer */
|
|
#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42003830UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
|
|
#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42003831UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
|
|
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
|
|
|
/* ========== Instance parameters for TC2 peripheral ========== */
|
|
#define TC2_CC_NUM 2
|
|
#define TC2_DMAC_ID_MC_0 34
|
|
#define TC2_DMAC_ID_MC_1 35
|
|
#define TC2_DMAC_ID_MC_LSB 34
|
|
#define TC2_DMAC_ID_MC_MSB 35
|
|
#define TC2_DMAC_ID_MC_SIZE 2
|
|
#define TC2_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
|
|
#define TC2_EXT 0
|
|
#define TC2_GCLK_ID 31
|
|
#define TC2_MASTER 1
|
|
#define TC2_OW_NUM 2
|
|
|
|
#endif /* _SAMC21_TC2_INSTANCE_ */
|