192 lines
10 KiB
C
192 lines
10 KiB
C
/**
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* \file
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*
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* \brief Component description for DIVAS
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMC21_DIVAS_COMPONENT_
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#define _SAMC21_DIVAS_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR DIVAS */
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/* ========================================================================== */
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/** \addtogroup SAMC21_DIVAS Divide and Square Root Accelerator */
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/*@{*/
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#define DIVAS_U2258
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#define REV_DIVAS 0x100
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/* -------- DIVAS_CTRLA : (DIVAS Offset: 0x00) (R/W 8) Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t SIGNED:1; /*!< bit: 0 Signed */
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uint8_t DLZ:1; /*!< bit: 1 Disable Leading Zero Optimization */
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uint8_t :6; /*!< bit: 2.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} DIVAS_CTRLA_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define DIVAS_CTRLA_OFFSET 0x00 /**< \brief (DIVAS_CTRLA offset) Control */
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#define DIVAS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DIVAS_CTRLA reset_value) Control */
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#define DIVAS_CTRLA_SIGNED_Pos 0 /**< \brief (DIVAS_CTRLA) Signed */
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#define DIVAS_CTRLA_SIGNED (_U_(0x1) << DIVAS_CTRLA_SIGNED_Pos)
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#define DIVAS_CTRLA_DLZ_Pos 1 /**< \brief (DIVAS_CTRLA) Disable Leading Zero Optimization */
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#define DIVAS_CTRLA_DLZ (_U_(0x1) << DIVAS_CTRLA_DLZ_Pos)
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#define DIVAS_CTRLA_MASK _U_(0x03) /**< \brief (DIVAS_CTRLA) MASK Register */
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/* -------- DIVAS_STATUS : (DIVAS Offset: 0x04) (R/W 8) Status -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t BUSY:1; /*!< bit: 0 DIVAS Accelerator Busy */
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uint8_t DBZ:1; /*!< bit: 1 Writing a one to this bit clears DBZ to zero */
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uint8_t :6; /*!< bit: 2.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} DIVAS_STATUS_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define DIVAS_STATUS_OFFSET 0x04 /**< \brief (DIVAS_STATUS offset) Status */
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#define DIVAS_STATUS_RESETVALUE _U_(0x00) /**< \brief (DIVAS_STATUS reset_value) Status */
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#define DIVAS_STATUS_BUSY_Pos 0 /**< \brief (DIVAS_STATUS) DIVAS Accelerator Busy */
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#define DIVAS_STATUS_BUSY (_U_(0x1) << DIVAS_STATUS_BUSY_Pos)
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#define DIVAS_STATUS_DBZ_Pos 1 /**< \brief (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero */
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#define DIVAS_STATUS_DBZ (_U_(0x1) << DIVAS_STATUS_DBZ_Pos)
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#define DIVAS_STATUS_MASK _U_(0x03) /**< \brief (DIVAS_STATUS) MASK Register */
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/* -------- DIVAS_DIVIDEND : (DIVAS Offset: 0x08) (R/W 32) Dividend -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t DIVIDEND:32; /*!< bit: 0..31 DIVIDEND */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} DIVAS_DIVIDEND_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define DIVAS_DIVIDEND_OFFSET 0x08 /**< \brief (DIVAS_DIVIDEND offset) Dividend */
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#define DIVAS_DIVIDEND_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_DIVIDEND reset_value) Dividend */
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#define DIVAS_DIVIDEND_DIVIDEND_Pos 0 /**< \brief (DIVAS_DIVIDEND) DIVIDEND */
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#define DIVAS_DIVIDEND_DIVIDEND_Msk (_U_(0xFFFFFFFF) << DIVAS_DIVIDEND_DIVIDEND_Pos)
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#define DIVAS_DIVIDEND_DIVIDEND(value) (DIVAS_DIVIDEND_DIVIDEND_Msk & ((value) << DIVAS_DIVIDEND_DIVIDEND_Pos))
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#define DIVAS_DIVIDEND_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_DIVIDEND) MASK Register */
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/* -------- DIVAS_DIVISOR : (DIVAS Offset: 0x0C) (R/W 32) Divisor -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t DIVISOR:32; /*!< bit: 0..31 DIVISOR */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} DIVAS_DIVISOR_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define DIVAS_DIVISOR_OFFSET 0x0C /**< \brief (DIVAS_DIVISOR offset) Divisor */
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#define DIVAS_DIVISOR_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_DIVISOR reset_value) Divisor */
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#define DIVAS_DIVISOR_DIVISOR_Pos 0 /**< \brief (DIVAS_DIVISOR) DIVISOR */
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#define DIVAS_DIVISOR_DIVISOR_Msk (_U_(0xFFFFFFFF) << DIVAS_DIVISOR_DIVISOR_Pos)
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#define DIVAS_DIVISOR_DIVISOR(value) (DIVAS_DIVISOR_DIVISOR_Msk & ((value) << DIVAS_DIVISOR_DIVISOR_Pos))
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#define DIVAS_DIVISOR_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_DIVISOR) MASK Register */
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/* -------- DIVAS_RESULT : (DIVAS Offset: 0x10) (R/ 32) Result -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t RESULT:32; /*!< bit: 0..31 RESULT */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} DIVAS_RESULT_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define DIVAS_RESULT_OFFSET 0x10 /**< \brief (DIVAS_RESULT offset) Result */
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#define DIVAS_RESULT_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_RESULT reset_value) Result */
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#define DIVAS_RESULT_RESULT_Pos 0 /**< \brief (DIVAS_RESULT) RESULT */
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#define DIVAS_RESULT_RESULT_Msk (_U_(0xFFFFFFFF) << DIVAS_RESULT_RESULT_Pos)
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#define DIVAS_RESULT_RESULT(value) (DIVAS_RESULT_RESULT_Msk & ((value) << DIVAS_RESULT_RESULT_Pos))
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#define DIVAS_RESULT_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_RESULT) MASK Register */
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/* -------- DIVAS_REM : (DIVAS Offset: 0x14) (R/ 32) Remainder -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t REM:32; /*!< bit: 0..31 REM */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} DIVAS_REM_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define DIVAS_REM_OFFSET 0x14 /**< \brief (DIVAS_REM offset) Remainder */
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#define DIVAS_REM_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_REM reset_value) Remainder */
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#define DIVAS_REM_REM_Pos 0 /**< \brief (DIVAS_REM) REM */
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#define DIVAS_REM_REM_Msk (_U_(0xFFFFFFFF) << DIVAS_REM_REM_Pos)
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#define DIVAS_REM_REM(value) (DIVAS_REM_REM_Msk & ((value) << DIVAS_REM_REM_Pos))
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#define DIVAS_REM_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_REM) MASK Register */
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/* -------- DIVAS_SQRNUM : (DIVAS Offset: 0x18) (R/W 32) Square Root Input -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t SQRNUM:32; /*!< bit: 0..31 Square Root Input */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} DIVAS_SQRNUM_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define DIVAS_SQRNUM_OFFSET 0x18 /**< \brief (DIVAS_SQRNUM offset) Square Root Input */
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#define DIVAS_SQRNUM_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_SQRNUM reset_value) Square Root Input */
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#define DIVAS_SQRNUM_SQRNUM_Pos 0 /**< \brief (DIVAS_SQRNUM) Square Root Input */
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#define DIVAS_SQRNUM_SQRNUM_Msk (_U_(0xFFFFFFFF) << DIVAS_SQRNUM_SQRNUM_Pos)
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#define DIVAS_SQRNUM_SQRNUM(value) (DIVAS_SQRNUM_SQRNUM_Msk & ((value) << DIVAS_SQRNUM_SQRNUM_Pos))
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#define DIVAS_SQRNUM_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_SQRNUM) MASK Register */
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/** \brief DIVAS hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO DIVAS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
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RoReg8 Reserved1[0x3];
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__IO DIVAS_STATUS_Type STATUS; /**< \brief Offset: 0x04 (R/W 8) Status */
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RoReg8 Reserved2[0x3];
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__IO DIVAS_DIVIDEND_Type DIVIDEND; /**< \brief Offset: 0x08 (R/W 32) Dividend */
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__IO DIVAS_DIVISOR_Type DIVISOR; /**< \brief Offset: 0x0C (R/W 32) Divisor */
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__I DIVAS_RESULT_Type RESULT; /**< \brief Offset: 0x10 (R/ 32) Result */
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__I DIVAS_REM_Type REM; /**< \brief Offset: 0x14 (R/ 32) Remainder */
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__IO DIVAS_SQRNUM_Type SQRNUM; /**< \brief Offset: 0x18 (R/W 32) Square Root Input */
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} Divas;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAMC21_DIVAS_COMPONENT_ */
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