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lis3dh: increase scale from 8g to 16g

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Signed-off-by: Luke Vuksta <wulfstawulfsta@gmail.com>
This commit is contained in:
Wulfsta
2025-04-04 18:18:29 -04:00
committed by KevinOConnor
parent 2e82fc4790
commit f1e0730701
1 changed files with 3 additions and 3 deletions
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6
klippy/extras/lis2dw.py
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@@ -34,7 +34,7 @@ LIS_I2C_ADDR = 0x19
# Right shift for left justified registers.
FREEFALL_ACCEL = 9.80665
LIS2DW_SCALE = FREEFALL_ACCEL * 1.952 / 4
LIS3DH_SCALE = FREEFALL_ACCEL * 3.906 / 16
LIS3DH_SCALE = FREEFALL_ACCEL * 11.718 / 16
BATCH_UPDATES = 0.100
@@ -167,8 +167,8 @@ class LIS2DW:
self.set_reg(REG_LIS2DW_CTRL_REG1_ADDR, 0x97)
# Disable all filtering
self.set_reg(REG_LIS2DW_CTRL_REG2_ADDR, 0)
# Set +-8g, High Resolution mode
self.set_reg(REG_LIS2DW_CTRL_REG4_ADDR, 0x28)
# Set +-16g, High Resolution mode
self.set_reg(REG_LIS2DW_CTRL_REG4_ADDR, 0x38)
# Enable FIFO
self.set_reg(REG_LIS2DW_CTRL_REG5_ADDR, 0x40)
# Stream mode