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stm32: Add STM32F429 variant (#3926)

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* Add F429 variant; add CAN on PD0,PD1; add 25Mhx clock; move CAN1_RX from PI8 to correct position (PI9)

* Add test for STM32F429

Signed-off-by: Arkadiusz Raj <arek.raj@gmail.com>
This commit is contained in:
Arek
2021-02-19 02:12:32 +01:00
committed by GitHub
parent 03b3cff823
commit e6d1910ef9
3 changed files with 25 additions and 9 deletions
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11
src/stm32/can.c
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@@ -28,8 +28,8 @@
#define GPIO_Tx GPIO('B', 9)
#endif
#if CONFIG_CAN_PINS_PI8_PH13
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PI8,PH13");
#define GPIO_Rx GPIO('I', 8)
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PI9,PH13");
#define GPIO_Rx GPIO('I', 9)
#define GPIO_Tx GPIO('H', 13)
#endif
#if CONFIG_CAN_PINS_PB5_PB6
@@ -42,6 +42,11 @@
#define GPIO_Rx GPIO('B', 12)
#define GPIO_Tx GPIO('B', 13)
#endif
#if CONFIG_CAN_PINS_PD0_PD1
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PD0,PD1");
#define GPIO_Rx GPIO('D', 0)
#define GPIO_Tx GPIO('D', 1)
#endif
#if CONFIG_MACH_STM32F0
#define SOC_CAN CAN
@@ -64,7 +69,7 @@
#if CONFIG_MACH_STM32F4
#warning CAN on STM32F4 is untested
#if (CONFIG_CAN_PINS_PA11_PA12 || CONFIG_CAN_PINS_PB8_PB9 \
|| CONFIG_CAN_PINS_PI8_PH13)
|| CONFIG_CAN_PINS_PD0_PD1 || CONFIG_CAN_PINS_PI9_PH13)
#define SOC_CAN CAN1
#define CAN_RX0_IRQn CAN1_RX0_IRQn
#define CAN_RX1_IRQn CAN1_RX1_IRQn