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stm32: Slow ADC frequency to 4.5Mhz

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There are reports that SKR mini boards have more stable ADC results
when running the ADC at a slower frequency.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
2020-04-21 10:23:14 -04:00
parent 1460e0d6f4
commit b6ebf5cb09
2 changed files with 4 additions and 4 deletions
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2
src/stm32/stm32f1.c
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@@ -140,7 +140,7 @@ clock_setup(void)
cfgr = ((0 << RCC_CFGR_PLLSRC_Pos)
| ((div2 - 2) << RCC_CFGR_PLLMULL_Pos));
}
cfgr |= RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV4;
cfgr |= RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8;
RCC->CFGR = cfgr;
RCC->CR |= RCC_CR_PLLON;