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stm32: add FDCAN support for STM32H743 (SKR-3 Series) (#5668)

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Signed-off-by: Chen.BJ from BigTreeTech <chenbj@biqu3d.com>
This commit is contained in:
BIGTREETECH
2022-08-24 05:53:35 +08:00
committed by GitHub
parent 9e4994cbdb
commit a8883d83e3
3 changed files with 85 additions and 8 deletions
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52
src/stm32/fdcan.c
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@@ -55,13 +55,25 @@ FDCAN_RAM_TypeDef *fdcan_ram = (FDCAN_RAM_TypeDef *)(SRAMCAN_BASE);
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB8,PB9");
#define GPIO_Rx GPIO('B', 8)
#define GPIO_Tx GPIO('B', 9)
#elif CONFIG_STM32_CANBUS_PD0_PD1
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PD0,PD1");
#define GPIO_Rx GPIO('D', 0)
#define GPIO_Tx GPIO('D', 1)
#elif CONFIG_STM32_CANBUS_PD12_PD13
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PD12,PD13");
#define GPIO_Rx GPIO('D', 12)
#define GPIO_Tx GPIO('D', 13)
#elif CONFIG_STM32_CANBUS_PB0_PB1
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB0,PB1");
#define GPIO_Rx GPIO('B', 0)
#define GPIO_Tx GPIO('B', 1)
#elif CONFIG_STM32_CANBUS_PC2_PC3
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PC2,PC3");
#define GPIO_Rx GPIO('C', 2)
#define GPIO_Tx GPIO('C', 3)
#endif
#if !CONFIG_STM32_CANBUS_PB0_PB1
#if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3)
#define SOC_CAN FDCAN1
#define MSG_RAM fdcan_ram->fdcan1
#else
@@ -69,8 +81,13 @@ FDCAN_RAM_TypeDef *fdcan_ram = (FDCAN_RAM_TypeDef *)(SRAMCAN_BASE);
#define MSG_RAM fdcan_ram->fdcan2
#endif
#define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn
#define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number
#if CONFIG_MACH_STM32G0
#define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn
#define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number
#elif CONFIG_MACH_STM32H7
#define CAN_IT0_IRQn FDCAN1_IT0_IRQn
#define CAN_FUNCTION GPIO_FUNCTION(9) // Alternative function mapping number
#endif
#ifndef SOC_CAN
#error No known CAN device for configured MCU
@@ -128,8 +145,14 @@ canbus_set_filter(uint32_t id)
can_filter(0, CANBUS_ID_ADMIN);
can_filter(1, id);
can_filter(2, id + 1);
#if CONFIG_MACH_STM32G0
SOC_CAN->RXGFC = ((id ? 3 : 1) << FDCAN_RXGFC_LSS_Pos
| 0x02 << FDCAN_RXGFC_ANFS_Pos);
#elif CONFIG_MACH_STM32H7
SOC_CAN->SIDFC |= (id ? 3 : 1) << FDCAN_SIDFC_LSS_Pos;
SOC_CAN->GFC = 0x02 << FDCAN_GFC_ANFS_Pos;
#endif
/* Leave the initialisation mode for the filter */
SOC_CAN->CCCR &= ~FDCAN_CCCR_CCE;
@@ -251,6 +274,29 @@ can_init(void)
SOC_CAN->NBTP = btr;
#if CONFIG_MACH_STM32H7
/*
The Message RAM of STM32H7 is settable
So we set it to be consistent with STM32G0
*/
uint32_t flssa = (uint32_t)&MSG_RAM - (uint32_t)&fdcan_ram->fdcan1;
uint32_t f0sa = flssa +
(((uint32_t)MSG_RAM.RXF0 - (uint32_t)MSG_RAM.FLS) / 4);
uint32_t tbsa = f0sa +
(((uint32_t)MSG_RAM.TXFIFO - (uint32_t)MSG_RAM.RXF0) / 4);
SOC_CAN->SIDFC = flssa << FDCAN_SIDFC_FLSSA_Pos;
SOC_CAN->RXF0C = ((f0sa << FDCAN_RXF0C_F0SA_Pos)
| (3 << FDCAN_RXF0C_F0S_Pos));
SOC_CAN->RXESC = ((7 << FDCAN_RXESC_F1DS_Pos)
| (7 << FDCAN_RXESC_F0DS_Pos));
SOC_CAN->TXBC = ((tbsa << FDCAN_TXBC_TBSA_Pos)
| (3 << FDCAN_TXBC_TFQS_Pos));
SOC_CAN->TXESC = 7 << FDCAN_TXESC_TBDS_Pos;
#endif
/* Leave the initialisation mode */
SOC_CAN->CCCR &= ~FDCAN_CCCR_CCE;
SOC_CAN->CCCR &= ~FDCAN_CCCR_INIT;