lib: Add hc32f460 definitions
Signed-off-by: Steven Gotthardt <gotthardt@gmail.com>
This commit is contained in:
Steven Gotthardt
committed by
Kevin O'Connor
Kevin O'Connor
parent
1e7057e917
commit
94cbf5ff48
282
lib/hc32f460/driver/src/hc32f460_sram.c
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282
lib/hc32f460/driver/src/hc32f460_sram.c
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/*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_sram.c
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**
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** A detailed description is available at
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** @link SramGroup Internal SRAM module description @endlink
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**
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** - 2018-10-17 CDT First version for Device Driver Library of SRAM.
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**
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******************************************************************************/
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32f460_sram.h"
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#include "hc32f460_utility.h"
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/**
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*******************************************************************************
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** \addtogroup SramGroup
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Local type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Local pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*! Parameter validity check for ECC/Parity error handling. */
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#define IS_VALID_ERR_OP(x) \
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( ((x) == SramNmi) || \
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((x) == SramReset))
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/*! Parameter validity check for SRAM ECC mode */
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#define IS_VALID_ECC_MD(x) \
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( ((x) == EccMode0) || \
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((x) == EccMode1) || \
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((x) == EccMode2) || \
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((x) == EccMode3))
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/*! Parameter validity check for SRAM Index */
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#define IS_VALID_INDEX(x) \
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( ((x) == Sram12Idx) || \
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((x) == Sram3Idx) || \
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((x) == SramHsIdx) || \
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((x) == SramRetIdx))
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/*! Parameter validity check for SRAM R/W wait cycle */
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#define IS_VALID_WAIT_CYCLE(x) \
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( ((x) == SramCycle1) || \
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((x) == SramCycle2) || \
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((x) == SramCycle3) || \
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((x) == SramCycle4) || \
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((x) == SramCycle5) || \
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((x) == SramCycle6) || \
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((x) == SramCycle7) || \
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((x) == SramCycle8))
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/*! Parameter validity check for SRAM error status */
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#define IS_VALID_ERR(x) \
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( ((x) == Sram3EccErr1) || \
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((x) == Sram3EccErr2) || \
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((x) == Sram12ParityErr) || \
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((x) == SramHSParityErr) || \
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((x) == SramRetParityErr))
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/*******************************************************************************
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* Global variable definitions (declared in header file with 'extern')
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******************************************************************************/
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/*******************************************************************************
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* Local function prototypes ('static')
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******************************************************************************/
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/*******************************************************************************
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* Local variable definitions ('static')
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******************************************************************************/
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/*******************************************************************************
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* Function implementation - global ('extern') and local ('static')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief SRAM read, write wait cycle register disable function
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**
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** \param None
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**
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** \retval Ok SRAM R/W wait cycle register disabled
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**
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******************************************************************************/
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en_result_t SRAM_WT_Disable(void)
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{
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M4_SRAMC->WTPR = 0x76u;
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return Ok;
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}
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/**
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*******************************************************************************
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** \brief SRAM read, write wait cycle register enable function
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**
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** \param None
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**
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** \retval Ok SRAM R/W wait cycle register enabled
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**
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******************************************************************************/
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en_result_t SRAM_WT_Enable(void)
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{
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M4_SRAMC->WTPR = 0x77u;
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return Ok;
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}
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/**
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*******************************************************************************
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** \brief SRAM ECC/Parity check register disable function
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**
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** \param None
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**
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** \retval Ok SRAM ECC/Parity check register disabled
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**
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******************************************************************************/
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en_result_t SRAM_CK_Disable(void)
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{
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M4_SRAMC->CKPR = 0x76u;
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return Ok;
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}
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/**
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*******************************************************************************
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** \brief SRAM ECC/Parity check register enable function
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**
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** \param None
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**
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** \retval Ok SRAM ECC/Parity check register enabled
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**
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******************************************************************************/
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en_result_t SRAM_CK_Enable(void)
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{
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M4_SRAMC->CKPR = 0x77u;
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return Ok;
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}
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/**
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*******************************************************************************
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** \brief Get SRAM ECC/Parity error status flag
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**
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** \param [in] enSramErrStatus SRAM error status, This parameter can be
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** some values of @ref en_sram_err_status_t
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**
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** \retval Set Corresponding error occurs
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** Reset Corresponding error not occurs
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**
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******************************************************************************/
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en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus)
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{
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DDL_ASSERT(IS_VALID_ERR(enSramErrStatus));
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if (true == !!(enSramErrStatus & M4_SRAMC->CKSR))
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{
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return Set;
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}
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else
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{
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return Reset;
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}
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}
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/**
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*******************************************************************************
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** \brief Clear SRAM ECC/Parity error status flag
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**
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** \param [in] enSramErrStatus SRAM error status, This parameter can be
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** some values of @ref en_sram_err_status_t
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**
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** \retval Ok Corresponding error flag be cleared
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** ErrorInvalidParameter Invalid parameter
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**
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******************************************************************************/
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en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus)
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{
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DDL_ASSERT(IS_VALID_ERR(enSramErrStatus));
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M4_SRAMC->CKSR |= enSramErrStatus;
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return Ok;
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}
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/**
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*******************************************************************************
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** \brief SRAM initialization
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**
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** \param [in] pstcSramConfig SRAM configure structure
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**
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** \retval Ok SRAM initialized
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** ErrorInvalidParameter Invalid parameter
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**
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******************************************************************************/
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en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig)
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{
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uint8_t i = 0u;
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uint8_t u8TmpIdx;
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en_result_t enRet = Ok;
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DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramRC));
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DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramWC));
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DDL_ASSERT(IS_VALID_ECC_MD(pstcSramConfig->enSramEccMode));
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DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramEccOp));
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DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramPyOp));
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u8TmpIdx = pstcSramConfig->u8SramIdx;
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if (0u == u8TmpIdx)
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{
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enRet = ErrorInvalidParameter;
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}
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else
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{
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SRAM_WT_Enable();
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SRAM_CK_Enable();
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for (i = 0u; i < 4u; i++)
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{
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if (true == (u8TmpIdx & 0x01u))
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{
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M4_SRAMC->WTCR |= (pstcSramConfig->enSramRC | \
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(pstcSramConfig->enSramWC << 4ul)) << (i * 8ul);
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}
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u8TmpIdx >>= 1u;
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}
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/* SRAM3 ECC config */
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if (pstcSramConfig->u8SramIdx & Sram3Idx)
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{
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M4_SRAMC->CKCR_f.ECCMOD = pstcSramConfig->enSramEccMode;
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M4_SRAMC->CKCR_f.ECCOAD = pstcSramConfig->enSramEccOp;
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}
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/* SRAM1/2/HS/Ret parity config */
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else
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{
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M4_SRAMC->CKCR_f.PYOAD = pstcSramConfig->enSramPyOp;
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}
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SRAM_WT_Disable();
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SRAM_CK_Disable();
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}
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return enRet;
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}
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/**
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*******************************************************************************
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** \brief SRAM de-initialization
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**
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** \param None
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**
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** \retval Ok SRAM de-initialized
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**
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******************************************************************************/
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en_result_t SRAM_DeInit(void)
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{
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/* SRAM R/W wait register */
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M4_SRAMC->WTPR = 0x77ul;
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M4_SRAMC->WTCR = 0ul;
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M4_SRAMC->WTPR = 0x76ul;
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/* SRAM check register */
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M4_SRAMC->CKPR = 0x77ul;
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M4_SRAMC->CKCR = 0ul;
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M4_SRAMC->CKPR = 0x76ul;
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/* SRAM status register */
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M4_SRAMC->CKSR = 0x1Ful;
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return Ok;
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}
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//@} // SramGroup
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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