stm32: Unify enable_pclock() code
Unify the handling of the enable_pclock() and is_enabled_pclock() code across all stm32 chips. All chips will now perform a peripheral reset on enable_pclock() (this is a change for stm32f0 and stm32h7). The enable_pclock() code will now also disable irqs during the enable. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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@@ -18,42 +18,19 @@
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 2)
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// Enable a peripheral clock
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void
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enable_pclock(uint32_t periph_base)
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// Map a peripheral address to its enable bits
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struct cline
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lookup_clock_line(uint32_t periph_base)
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{
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if (periph_base < APB2PERIPH_BASE) {
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uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400;
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RCC->APB1ENR |= (1<<pos);
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RCC->APB1ENR;
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RCC->APB1RSTR |= (1<<pos);
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RCC->APB1RSTR &= ~(1<<pos);
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} else if (periph_base < AHBPERIPH_BASE) {
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uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400;
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RCC->APB2ENR |= (1<<pos);
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RCC->APB2ENR;
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RCC->APB2RSTR |= (1<<pos);
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RCC->APB2RSTR &= ~(1<<pos);
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if (periph_base >= AHBPERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - AHBPERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHBENR, .bit=bit};
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} else if (periph_base >= APB2PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - APB2PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit};
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} else {
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uint32_t pos = (periph_base - AHBPERIPH_BASE) / 0x400;
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RCC->AHBENR |= (1<<pos);
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RCC->AHBENR;
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}
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}
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// Check if a peripheral clock has been enabled
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int
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is_enabled_pclock(uint32_t periph_base)
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{
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if (periph_base < APB2PERIPH_BASE) {
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uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400;
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return RCC->APB1ENR & (1<<pos);
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} else if (periph_base < AHBPERIPH_BASE) {
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uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400;
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return RCC->APB2ENR & (1<<pos);
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} else {
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uint32_t pos = (periph_base - AHBPERIPH_BASE) / 0x400;
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return RCC->AHBENR & (1<<pos);
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uint32_t bit = 1 << ((periph_base - APB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB1ENR, .rst=&RCC->APB1RSTR, .bit=bit};
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}
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}
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