stm32: Add hardware PWM support for STM32F1
This adds hardware PWM support for STM32F1 processors. This should also work for STM32 F0/F2/F4 processors, but I don't have one of those to test it. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Michael Kurz
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Kevin O'Connor
Kevin O'Connor
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39188e1cf3
commit
59c4c49893
142
src/stm32/hard_pwm.c
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142
src/stm32/hard_pwm.c
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// Hardware PWM support on stm32
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//
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// Copyright (C) 2021 Michael Kurz <michi.kurz@gmail.com>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "board/irq.h" // irq_save
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#include "command.h" // shutdown
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#include "gpio.h" // gpio_pwm_write
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#include "internal.h" // GPIO
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#include "sched.h" // sched_shutdown
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#define MAX_PWM 255
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DECL_CONSTANT("PWM_MAX", MAX_PWM);
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struct gpio_pwm_info {
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TIM_TypeDef* timer;
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uint8_t pin, channel, function;
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};
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static const struct gpio_pwm_info pwm_regs[] = {
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{TIM2, GPIO('A', 0), 1, GPIO_FUNCTION(2)},
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{TIM2, GPIO('A', 1), 2, GPIO_FUNCTION(2)},
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{TIM2, GPIO('A', 2), 3, GPIO_FUNCTION(2)},
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{TIM2, GPIO('A', 3), 4, GPIO_FUNCTION(2)},
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{TIM2, GPIO('A', 15), 1, GPIO_FUNCTION(1)},
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{TIM2, GPIO('B', 3), 2, GPIO_FUNCTION(1)},
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{TIM2, GPIO('B', 10), 3, GPIO_FUNCTION(1)},
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{TIM2, GPIO('B', 11), 4, GPIO_FUNCTION(1)},
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{TIM3, GPIO('A', 6), 1, GPIO_FUNCTION(1)},
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{TIM3, GPIO('A', 7), 2, GPIO_FUNCTION(1)},
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{TIM3, GPIO('B', 0), 3, GPIO_FUNCTION(1)},
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{TIM3, GPIO('B', 1), 4, GPIO_FUNCTION(1)},
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{TIM3, GPIO('C', 6), 1, GPIO_FUNCTION(2)},
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{TIM3, GPIO('C', 7), 2, GPIO_FUNCTION(2)},
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{TIM3, GPIO('C', 8), 3, GPIO_FUNCTION(2)},
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{TIM3, GPIO('C', 9), 4, GPIO_FUNCTION(2)},
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{TIM4, GPIO('D', 12), 1, GPIO_FUNCTION(2)},
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{TIM4, GPIO('D', 13), 2, GPIO_FUNCTION(2)},
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{TIM4, GPIO('D', 14), 3, GPIO_FUNCTION(2)},
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{TIM4, GPIO('D', 15), 4, GPIO_FUNCTION(2)},
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{TIM4, GPIO('B', 6), 1, GPIO_FUNCTION(2)},
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{TIM4, GPIO('B', 7), 2, GPIO_FUNCTION(2)},
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{TIM4, GPIO('B', 8), 3, GPIO_FUNCTION(2)},
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{TIM4, GPIO('B', 9), 4, GPIO_FUNCTION(2)}
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};
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struct gpio_pwm
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gpio_pwm_setup(uint8_t pin, uint32_t cycle_time, uint8_t val){
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// Find pin in pwm_regs table
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const struct gpio_pwm_info* p = pwm_regs;
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for (;; p++) {
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if (p >= &pwm_regs[ARRAY_SIZE(pwm_regs)])
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shutdown("Not a valid PWM pin");
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if (p->pin == pin)
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break;
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}
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// Map cycle_time to pwm clock divisor
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uint32_t pclk = get_pclock_frequency((uint32_t)p->timer);
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uint32_t pclock_div = CONFIG_CLOCK_FREQ / pclk;
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if (pclock_div > 1)
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pclock_div /= 2; // Timers run at twice the normal pclock frequency
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uint32_t prescaler = cycle_time / (pclock_div * (MAX_PWM - 1));
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if (prescaler > 0) {
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prescaler -= 1;
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} else if (prescaler > UINT16_MAX) {
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prescaler = UINT16_MAX;
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}
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gpio_peripheral(p->pin, p->function, 0);
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// Enable clock
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if (!is_enabled_pclock((uint32_t) p->timer)) {
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enable_pclock((uint32_t) p->timer);
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}
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if (p->timer->CR1 & TIM_CR1_CEN) {
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if (p->timer->PSC != (uint16_t) prescaler) {
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shutdown("PWM already programmed at different speed");
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}
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} else {
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p->timer->PSC = (uint16_t) prescaler;
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p->timer->ARR = MAX_PWM - 1;
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p->timer->EGR |= TIM_EGR_UG;
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}
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struct gpio_pwm channel;
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switch (p->channel) {
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case 1: {
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channel.reg = (void*) &p->timer->CCR1;
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p->timer->CCER &= ~TIM_CCER_CC1E;
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p->timer->CCMR1 &= ~(TIM_CCMR1_OC1M | TIM_CCMR1_CC1S);
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p->timer->CCMR1 |= (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
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TIM_CCMR1_OC1PE | TIM_CCMR1_OC1FE);
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gpio_pwm_write(channel, val);
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p->timer->CCER |= TIM_CCER_CC1E;
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break;
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}
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case 2: {
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channel.reg = (void*) &p->timer->CCR2;
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p->timer->CCER &= ~TIM_CCER_CC2E;
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p->timer->CCMR1 &= ~(TIM_CCMR1_OC2M | TIM_CCMR1_CC2S);
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p->timer->CCMR1 |= (TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 |
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TIM_CCMR1_OC2PE | TIM_CCMR1_OC2FE);
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gpio_pwm_write(channel, val);
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p->timer->CCER |= TIM_CCER_CC2E;
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break;
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}
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case 3: {
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channel.reg = (void*) &p->timer->CCR3;
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p->timer->CCER &= ~TIM_CCER_CC3E;
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p->timer->CCMR2 &= ~(TIM_CCMR2_OC3M | TIM_CCMR2_CC3S);
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p->timer->CCMR2 |= (TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
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TIM_CCMR2_OC3PE | TIM_CCMR2_OC3FE);
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gpio_pwm_write(channel, val);
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p->timer->CCER |= TIM_CCER_CC3E;
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break;
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}
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case 4: {
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channel.reg = (void*) &p->timer->CCR4;
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p->timer->CCER &= ~TIM_CCER_CC4E;
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p->timer->CCMR2 &= ~(TIM_CCMR2_OC4M | TIM_CCMR2_CC4S);
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p->timer->CCMR2 |= (TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 |
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TIM_CCMR2_OC4PE | TIM_CCMR2_OC4FE);
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gpio_pwm_write(channel, val);
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p->timer->CCER |= TIM_CCER_CC4E;
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break;
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}
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default:
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shutdown("Invalid PWM channel");
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}
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// Enable PWM output
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p->timer->CR1 |= TIM_CR1_CEN;
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return channel;
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}
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void
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gpio_pwm_write(struct gpio_pwm g, uint32_t val) {
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*(volatile uint32_t*) g.reg = val;
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}
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