From 5001983d349ef1a1608e2c884888b9040f80ef89 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Fri, 18 Apr 2025 21:23:21 -0400 Subject: [PATCH] stm32: Fix pll_base on stm32h7 when using a clock other than 25Mhz Signed-off-by: Kevin O'Connor --- src/stm32/stm32h7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c index 387e47dd9..d3e70c793 100644 --- a/src/stm32/stm32h7.c +++ b/src/stm32/stm32h7.c @@ -100,7 +100,7 @@ clock_setup(void) ; // (HSE 25mhz) /DIVM1(5) (pll_base 5Mhz) *DIVN1(192) (pll_freq 960Mhz) // /DIVP1(2) (SYSCLK 480Mhz) - uint32_t pll_base = 5000000; + uint32_t pll_base = CONFIG_STM32_CLOCK_REF_25M ? 5000000 : 4000000; // Only even dividers (DIVP1) are allowed uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2; if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {