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stm32: Add stm32h7 SPI support (#4850)

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Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
This commit is contained in:
adelyser
2021-11-20 16:23:23 -07:00
committed by GitHub
parent b480734c88
commit 3ac354088a
3 changed files with 159 additions and 3 deletions
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8
src/stm32/stm32h7.c
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@@ -5,7 +5,7 @@
// This file may be distributed under the terms of the GNU GPLv3 license.
// USB and I2C is not supported, SPI is untested!
// I2C is not supported
#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
#include "board/armcm_boot.h" // VectorTable
@@ -170,7 +170,10 @@ clock_setup(void)
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE_Msk, RCC_PLLCFGR_PLL1RGE_2);
// Disable unused PLL1 outputs
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN_Msk, 0);
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN_Msk, 0);
// Enable PLL1Q and set to 100MHz for SPI 1,2,3
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN, RCC_PLLCFGR_DIVQ1EN);
MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1,
(pll_freq / FREQ_PERIPH - 1) << RCC_PLL1DIVR_Q1_Pos);
// This is necessary, default is not 1!
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN_Msk, RCC_PLLCFGR_DIVP1EN);
// Set multiplier DIVN1 and post divider DIVP1
@@ -184,6 +187,7 @@ clock_setup(void)
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS_Msk, PWR_D3CR_VOS);
while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
;
// Enable VOS0 (overdrive)
if (CONFIG_CLOCK_FREQ > 400000000) {
RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;