Makefile: Reduce use of $^ in build rules
It's rare to use all of a target's prerequisites in a recipe - replace most cases with $< (the target's first prerequisite). Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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@@ -31,7 +31,7 @@ $(OUT)pru0.elf: $(patsubst %.c, $(OUT)src/%.o,$(pru0-y))
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$(OUT)pru1.elf: $(OUT)klipper.elf
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@echo " Linking $@"
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$(Q)$(CC) $(CFLAGS_pru1.elf) $^ -o $@
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$(Q)$(CC) $(CFLAGS_pru1.elf) $< -o $@
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flash: $(OUT)pru0.elf $(OUT)pru1.elf
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@echo " Flashing"
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