Makefile: Reduce use of $^ in build rules

It's rare to use all of a target's prerequisites in a recipe - replace
most cases with $< (the target's first prerequisite).

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
2019-03-02 12:01:44 -05:00
parent 9430fea2c5
commit 399d539969
5 changed files with 9 additions and 9 deletions

View File

@@ -31,7 +31,7 @@ $(OUT)pru0.elf: $(patsubst %.c, $(OUT)src/%.o,$(pru0-y))
$(OUT)pru1.elf: $(OUT)klipper.elf
@echo " Linking $@"
$(Q)$(CC) $(CFLAGS_pru1.elf) $^ -o $@
$(Q)$(CC) $(CFLAGS_pru1.elf) $< -o $@
flash: $(OUT)pru0.elf $(OUT)pru1.elf
@echo " Flashing"