lib: Add bossac 1.9 code to lib directory
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
347
lib/bossac/src/D2xNvmFlash.cpp
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347
lib/bossac/src/D2xNvmFlash.cpp
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///////////////////////////////////////////////////////////////////////////////
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// BOSSA
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//
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// Copyright (c) 2018, ShumaTech
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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///////////////////////////////////////////////////////////////////////////////
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#include "D2xNvmFlash.h"
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// CMDEX field should be 0xA5 to allow execution of any command.
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#define CMDEX_KEY 0xa500
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// NVM ready bit mask
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#define NVM_INT_STATUS_READY_MASK 0x1
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// NVM status mask
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#define NVM_CTRL_STATUS_MASK 0xFFEB
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#define NVM_REG_BASE 0x41004000
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#define NVM_REG_CTRLA 0x00
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#define NVM_REG_CTRLB 0x04
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#define NVM_REG_INTFLAG 0x14
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#define NVM_REG_STATUS 0x18
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#define NVM_REG_ADDR 0x1c
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#define NVM_REG_LOCK 0x20
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#define NVM_CMD_ER 0x02
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#define NVM_CMD_WP 0x04
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#define NVM_CMD_EAR 0x05
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#define NVM_CMD_WAP 0x06
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#define NVM_CMD_LR 0x40
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#define NVM_CMD_UR 0x41
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#define NVM_CMD_SSB 0x45
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#define NVM_CMD_PBC 0x44
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#define ERASE_ROW_PAGES 4 // pages
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// NVM User Row
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#define NVM_UR_ADDR 0x804000
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#define NVM_UR_SIZE (_size * ERASE_ROW_PAGES)
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#define NVM_UR_BOD33_ENABLE_OFFSET 0x1
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#define NVM_UR_BOD33_ENABLE_MASK 0x6
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#define NVM_UR_BOD33_RESET_OFFSET 0x1
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#define NVM_UR_BOD33_RESET_MASK 0x7
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#define NVM_UR_NVM_LOCK_OFFSET 0x6
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D2xNvmFlash::D2xNvmFlash(
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Samba& samba,
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const std::string& name,
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uint32_t pages,
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uint32_t size,
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uint32_t user,
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uint32_t stack)
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:
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Flash(samba, name, 0, pages, size, 1, 16, user, stack), _eraseAuto(true)
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{
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}
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D2xNvmFlash::~D2xNvmFlash()
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{
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}
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void
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D2xNvmFlash::erase(uint32_t offset, uint32_t size)
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{
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uint32_t eraseSize = _size * ERASE_ROW_PAGES;
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// Offset must be a multiple of the erase size
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if (offset % eraseSize)
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throw FlashEraseError();
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// Offset and size must be in range
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if (offset + size > totalSize())
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throw FlashEraseError();
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uint32_t eraseEnd = (offset + size + eraseSize - 1) / eraseSize;
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// Erase each erase size set of pages
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for (uint32_t eraseNum = offset / eraseSize; eraseNum < eraseEnd; eraseNum++)
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{
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waitReady();
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// Clear error bits
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uint16_t statusReg = readReg(NVM_REG_STATUS);
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writeReg(NVM_REG_STATUS, statusReg | NVM_CTRL_STATUS_MASK);
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// Issue erase command
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uint32_t wordAddr = (eraseNum * eraseSize) / 2;
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writeReg(NVM_REG_ADDR, wordAddr);
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command(NVM_CMD_ER);
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}
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}
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void
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D2xNvmFlash::eraseAll(uint32_t offset)
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{
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// Use the extended Samba command if available
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if (_samba.canChipErase())
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{
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_samba.chipErase(offset);
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}
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else
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{
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erase(offset, totalSize() - offset);
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}
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}
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void
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D2xNvmFlash::eraseAuto(bool enable)
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{
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_eraseAuto = enable;
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}
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std::vector<bool>
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D2xNvmFlash::getLockRegions()
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{
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uint8_t lockBits = 0;
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uint32_t addr = NVM_UR_ADDR + NVM_UR_NVM_LOCK_OFFSET;
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std::vector<bool> regions(_lockRegions);
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for (uint32_t region = 0; region < _lockRegions; region++)
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{
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if (region % 8 == 0)
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lockBits = _samba.readByte(addr++);
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regions[region] = (lockBits & (1 << (region % 8))) == 0;
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}
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return regions;
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}
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bool
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D2xNvmFlash::getSecurity()
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{
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return (readReg(NVM_REG_STATUS) & 0x100) != 0;
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}
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bool
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D2xNvmFlash::getBod()
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{
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uint8_t byte = _samba.readByte(NVM_UR_ADDR + NVM_UR_BOD33_ENABLE_OFFSET);
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return (byte & NVM_UR_BOD33_ENABLE_MASK) != 0;
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}
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bool
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D2xNvmFlash::getBor()
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{
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uint8_t byte = _samba.readByte(NVM_UR_ADDR + NVM_UR_BOD33_RESET_OFFSET);
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return (byte & NVM_UR_BOD33_RESET_MASK) != 0;
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}
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bool
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D2xNvmFlash::getBootFlash()
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{
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return true;
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}
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void
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D2xNvmFlash::readUserRow(std::unique_ptr<uint8_t[]>& userRow)
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{
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if (!userRow)
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{
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userRow.reset(new uint8_t[NVM_UR_SIZE]);
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_samba.read(NVM_UR_ADDR, userRow.get(), NVM_UR_SIZE);
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}
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}
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void
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D2xNvmFlash::writeOptions()
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{
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std::unique_ptr<uint8_t[]> userRow;
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if (canBor() && _bor.isDirty() && _bor.get() != getBor())
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{
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readUserRow(userRow);
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if (_bor.get())
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userRow[NVM_UR_BOD33_RESET_OFFSET] |= NVM_UR_BOD33_RESET_MASK;
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else
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userRow[NVM_UR_BOD33_RESET_OFFSET] &= ~NVM_UR_BOD33_RESET_MASK;
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}
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if (canBod() && _bod.isDirty() && _bod.get() != getBod())
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{
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readUserRow(userRow);
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if (_bod.get())
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userRow[NVM_UR_BOD33_ENABLE_OFFSET] |= NVM_UR_BOD33_ENABLE_MASK;
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else
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userRow[NVM_UR_BOD33_ENABLE_OFFSET] &= ~NVM_UR_BOD33_ENABLE_MASK;
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}
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if (_regions.isDirty())
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{
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// Check if any lock bits are different from the current set
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std::vector<bool> current = getLockRegions();
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if (!equal(_regions.get().begin(), _regions.get().end(), current.begin()))
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{
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readUserRow(userRow);
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uint8_t* lockBits = &userRow[NVM_UR_NVM_LOCK_OFFSET];
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for (uint32_t region = 0; region < _regions.get().size(); region++)
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{
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if (_regions.get()[region])
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lockBits[region / 8] &= ~(1 << (region % 8));
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else
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lockBits[region / 8] |= (1 << (region % 8));
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}
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}
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}
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// Erase and write the user row if modified
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if (userRow)
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{
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// Disable cache and configure manual page write
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writeReg(NVM_REG_CTRLB, readReg(NVM_REG_CTRLB) | (0x1 << 18) | (0x1 << 7));
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// Erase user row
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writeReg(NVM_REG_ADDR, NVM_UR_ADDR / 2);
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command(NVM_CMD_EAR);
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// Write user row in page chunks
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for (uint32_t offset = 0; offset < NVM_UR_SIZE; offset += _size)
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{
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// Load the buffer with the page
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loadBuffer(&userRow[offset], _size);
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// Clear page buffer
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command(NVM_CMD_PBC);
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// Copy page to page buffer
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_wordCopy.setDstAddr(NVM_UR_ADDR + offset);
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_wordCopy.setSrcAddr(_onBufferA ? _pageBufferA : _pageBufferB);
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_onBufferA = !_onBufferA;
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waitReady();
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_wordCopy.runv();
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// Write the page
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writeReg(NVM_REG_ADDR, (NVM_UR_ADDR + offset) / 2);
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command(NVM_CMD_WAP);
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}
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}
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// Always do security last
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if (_security.isDirty() && _security.get() == true && _security.get() != getSecurity())
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{
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command(NVM_CMD_SSB);
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}
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}
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void
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D2xNvmFlash::writePage(uint32_t page)
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{
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if (page >= _pages)
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{
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throw FlashPageError();
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}
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// Disable cache and configure manual page write
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writeReg(NVM_REG_CTRLB, readReg(NVM_REG_CTRLB) | (0x1 << 18) | (0x1 << 7));
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// Auto-erase if writing at the start of the erase page
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if (_eraseAuto && page % ERASE_ROW_PAGES == 0)
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erase(page * _size, ERASE_ROW_PAGES * _size);
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// Clear page buffer
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command(NVM_CMD_PBC);
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// Compute the start address.
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uint32_t addr = _addr + (page * _size);
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_wordCopy.setDstAddr(addr);
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_wordCopy.setSrcAddr(_onBufferA ? _pageBufferA : _pageBufferB);
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_onBufferA = !_onBufferA;
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waitReady();
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_wordCopy.runv();
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writeReg(NVM_REG_ADDR, addr / 2);
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command(NVM_CMD_WP);
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}
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void
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D2xNvmFlash::waitReady()
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{
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while ((readReg(NVM_REG_INTFLAG) & 0x1) == 0);
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}
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void
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D2xNvmFlash::readPage(uint32_t page, uint8_t* buf)
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{
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if (page >= _pages)
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{
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throw FlashPageError();
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}
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_samba.read(_addr + (page * _size), buf, _size);
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}
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uint32_t
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D2xNvmFlash::readReg(uint8_t reg)
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{
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return _samba.readWord(NVM_REG_BASE + reg);
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}
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void
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D2xNvmFlash::writeReg(uint8_t reg, uint32_t value)
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{
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_samba.writeWord(NVM_REG_BASE + reg, value);
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}
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void
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D2xNvmFlash::command(uint8_t cmd)
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{
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waitReady();
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writeReg(NVM_REG_CTRLA, CMDEX_KEY | cmd);
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waitReady();
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if (readReg(NVM_REG_INTFLAG) & 0x2)
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{
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// Clear the error bit
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writeReg(NVM_REG_INTFLAG, 0x2);
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throw FlashCmdError();
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}
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}
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void
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D2xNvmFlash::writeBuffer(uint32_t dst_addr, uint32_t size)
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{
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// Auto-erase if enabled
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if (_eraseAuto)
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erase(dst_addr, size);
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// Call the base class method
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Flash::writeBuffer(dst_addr, size);
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}
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