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stm32: Add comments on PLL frequency requirements to clock setup code

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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Kevin O'Connor
2025-05-31 17:00:18 -04:00
parent c0ca4c5cc7
commit 105ce35e1b
9 changed files with 22 additions and 0 deletions
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5
src/stm32/stm32f4.c
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@@ -57,6 +57,11 @@ gpio_clock_enable(GPIO_TypeDef *regs)
RCC->AHB1ENR;
}
// PLL (f207) input: 0.95 to 2.1Mhz, vco: 192 to 432Mhz, output: 24 to 120Mhz
// PLL (f401) input: 0.95 to 2.1Mhz, vco: 192 to 432Mhz, output: 24 to 84Mhz
// PLL (f405/7) input: 0.95 to 2.1Mhz, vco: 100 to 432Mhz, output: 24 to 168Mhz
// PLL (f446) input: 0.95 to 2.1Mhz, vco: 100 to 432Mhz, output: 12.5 to 180Mhz
#if !CONFIG_STM32_CLOCK_REF_INTERNAL
DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
#endif