stm32: Add comments on PLL frequency requirements to clock setup code

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
2025-05-31 17:00:18 -04:00
parent c0ca4c5cc7
commit 105ce35e1b
9 changed files with 22 additions and 0 deletions
--- a/src/stm32/stm32f1.c
+++ b/src/stm32/stm32f1.c
@@ -51,6 +51,8 @@ gpio_clock_enable(GPIO_TypeDef *regs)
    RCC->APB2ENR;
 }

+// PLL (f103) input: 1 to 25Mhz, output: 16 to 72Mhz
+
 // Main clock setup called at chip startup
 static void
 clock_setup(void)